### New Majority Gate Based Parallel BCD Adder Designs for Quantum-dot Cellular Automata

__New Majority Gate Based Parallel BCD Adder Designs for Quantum-dot Cellular Automata__

__New Majority Gate Based Parallel BCD Adder Designs for Quantum-dot Cellular Automata__

__ABSTRACT:__

In this paper, we first theoretically re-defined output decimal carry in terms of majority gates and proposed a carry look ahead structure for calculating all the intermediate output carries. We have used this method for designing the multi-digit decimal adders. Theoretically, our best n-digit decimal adder design reduces the delay and area-delay product (ADP) by 50% compared with previous designs. We have implemented our designs using QCA Designer tool. The proposed QCA Designer based 8-digit PBA-BCD adder achieves over 38% less delay compared with the best existing designs.

__EXISTING SYSTEM:__

The decimal arithmetic has received wide attention in response to the increasing demand for precision in financial and commercial based applications. Several digital processors and computers were designed including decimal arithmetic hardware units. The current CMOS technology is approaching its scaling limitation. New nanotechnologies including quantum-dot cellular automata (QCA), nano magnetic Logic (NML), and spin-wave devices (SWD) are studied due to their advantages in terms of low power and high density. These emerging nanotechnologies are based on majority logic, which is different from conventional Boolean logic in CMOS.

Figure 1 : Block diagram of 1-digit BCD adder

As the core of decimal arithmetic, previous works have been conducted into majority-based parallel decimal adders. The existing majority logic based parallel decimal adders mostly share the same structure, but differ from each other in the usage of binary adders. The 1-digit ripple carry adder (RCA) based BCD adders are proposed. However, these designs can be further optimized to reduce hardware complexity. Carry flow adder (CFA) based and carry look ahead adder (CLA) based BCD adders are presented, which show good performance. Moreover, exploits novel binary adder to propose the efficient 1-digit BCD adder, reducing comprehensive consumption. In order to fully utilize the majority gates, rewrite the correction function for less majority gates. Different from the existing designs, we use a new approach to compute carry logic in the multi-digit BCD adder.

In this paper, we propose a new definition for BCD adder output carry computation in terms of majority gates and use it for computing all the carries of the multi-digit BCD adder in parallel. We have introduced decimal group generate and decimal group propagate signals to calculate carries in the BCD adder. As a result, we have reduced delay in the multi digit BCD adder. We have used different types of binary adders, such as RCA, CFA and parallel binary adder (PBA) for realizing the proposed multi-digit BCD adder. Theoretically, our PBA based n-digit BCD adder reduces the delay and area-delay product (ADP) by 50% compared with the existing designs.

Figure 2 Block diagram of 4-digit BCD adder.

We have implemented our designs using QCA technology and designed using QCA Designer. The proposed QCA Designer based 8-digit PBA-BCD adder achieves at least 38% less delay compared with the best existing designs.

Fig. 1 shows the block diagram of conventional 1-digit BCD adder. The 1-digit BCD adder consists of 4-bit binary adder (ADD1), correction logic (CL) and 4-bit binary adder (ADD2). The binary adder (ADD1) adds the decimal number dA3:0, dB3:0 and dCin to produce the binary sum bS3:0 and output carry bCout. The CL circuit produces the cL3:0 and decimal output carry signals dCout for converting binary sum bS3:0 to decimal sum dS3:0. The cL3:0 = (0110)2, if dCout = 1 otherwise cL3:0 = (0000)2. The binary adder (ADD2) produces decimal digit dS3:0 by adding bS3:0 and cL3:0.

The theoretical delay required for generating 1-digit BCD adder dCout signal (dc(1)) and dS3:0 signal (d(1)) are given in (1) and (2).

where da1, dcl and da2 represent the delays required for single ADD1, CL and ADD2 blocks, respectively.

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__DISADVANTAGES:__

- More power
- Low Density
- More delay

__PROPOSED SYSTEM:__

The block diagram of parallel 1-digit BCD circuit is shown in Fig. 3. The design in [12] used the same block diagram for the implementation of BCD adder but they have used ANDOR gate based output carry as shown in (6).

dCout = bCout + (bS3:0 >= 10) + (bS3:0 == 9)dCin (6)

We are going to define the dCout in terms of majority gates. For this, we rewrite (6) as follows:

dCout = bCout + (bS3:0 >= 10) + (bS3:0 >= 9)dCin

= bCout + (bS3:0 >= 10) + [bCout + (bS3:0 >= 9)]dCin (7)

Figure 3: Proposed block diagram of 1-digit BCD adder.

The logic signals bCout + (bS3:0 >= 10) and bCout + (bS3:0 >= 9) can be rewritten as [bCout + (bS3:0 >= 10)] · [bCout + (bS3:0 >= 9)] and [bCout + (bS3:0 >= 10)] + [bCout + (bS3:0 >= 9)], respectively. By substituting these values in dCout, we can rewrite the equation of dCout as follows:

dCout = [bCout + (bS3:0 >= 10)] · [bCout + (bS3:0 >= 9)] + [bCout + (bS3:0 >= 10) + bCout + (bS3:0 >= 9)]dCin (8)

The dCout in (8) is clearly in 3-input majority gate form with inputs bCout + (bS3:0 >= 10), bCout + (bS3:0 >= 9) and dCin. We can write the dCout using the majority gate as shown in (9).

dCout = M(bCout + (bS3:0 >= 10), bCout + (bS3:0 >= 9), dCin) (9)

The terms (bS3:0 >= 10) and (bS3:0 >= 9) are binary signals and we are calling these signals as decimal group generate and decimal group propagate signals. These two signals are represented as dG3:0 and dP3:0, as shown in (10) and (11), respectively

dG3:0 = bCout + (bS3:0 >= 10) (10)

dP3:0 = bCout + (bS3:0 >= 9) (11)

The proposed majority gate form of dCout using dG3:0 and dP3:0 signals is given as follows:.

dCout = M(dG3:0, dP3:0, dCin) (12)

The dCout in (12) uses decimal group generate and decimal group propagate signals for calculation. This is similar to CLA method for the calculation of carry. Because of this, we are calling CL stage as CL-CLA. The cL3:0 signal is calculated using the dCout as shown in (13).

cL3:0 = {0, dCout, dCout, 0} (13)

The proposed dCout in (12) requires only 1 majority gate after calculating the dG3:0 and dP3:0 signals. Fig. 4 shows the majority gate diagram of proposed dCout in (12). We have used the majority gate results presented in [10] for calculation of dG3:0, as shown in (14).

dG3:0 = bCout + bS3 · bS2 + bS3 · bS1 = M(bCout, M(bCout, bS3, 1), M(bS3, bS2, bS1)) (14)

To save the area, we have calculated dP3:0 as follows:

dP3:0 = bCout + (bS3:0 >= 9)

= bCout + (bS3:0 >= 10) + (bS3:0 == 9)

= dG3:0 + bS3 · bS0 (15)

We can observe that the decimal group generate and decimal group propagate signals are independent of decimal input carry, which are produced parallelly in the multi-digit BCD adder. Consequently, all decimal group generate and decimal group propagate signals of the multi-digit BCD adder share the same delay. Fig. 5 shows the majority gate circuit for calculating the carries dC1, dC2, dC3 and dC4 using decimal group generate and decimal group propagate signals. The delay required for calculating the dC4 in Fig. 5 is only the delay of four majority gates, which can be achieved from the proposed definition of dCout in (12).

__ADVANTAGES:__

- Low power
- High Density
- Low delay

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__REFERENCES:__

[1] L. K. Wang, M. J. Schulte, J. D. Thompson, and N. Jairam, “Hardware designs for decimal floating-point addition and related operations,” IEEE Transactions on Computers, vol. 58, no. 3, pp. 322-335, 2009.