ieee projects for ece 2017

IEEE Projects for ECE 2017


A System for Monitoring Hand Hygiene Compliance based-on Internet-of-Things

Agricultural Crop Monitoring using IOT- A Study

An Autonomous Wireless Body Area Network Implementation Towards IoT Connected Healthcare Applications

Analysis of Three IoT-Based Wireless Sensors for Environmental Monitoring

Child Safety Wearable Device

Connecting physical things to a SmartCity-OS

Decentralized Configuration of Embedded Web Services for Smart Home Applications

Design of Online Monitoring Device for COD Parameter in Industrial Sewage Based on Soft Measurement Method

Developing Portable Instrument Based on Internet of Things for Air Quality Information System

Efficient Low Cost Supervisory System for Internet of Things Enabled Smart Home

EMACS: Design and Implementation of Indoor Environment Monitoring and Control System

Energy Autonomous Wireless Valve Leakage Monitoring System With Acoustic Emission Sensor

First step towards an IoT implementation of a wireless sensors network for environmental radiation monitoring

Health Care Monitoring System in Internet of Things (loT) by Using RFID

Internet-of-things based Smart Tracking

Real-Time Signal Quality-Aware ECG Telemetry System for IoT-Based Health Care Monitoring

Room Temperature Control and Fire Alarm/Suppression IoT Service Using MQTT on AWS

We-Care: An IoT-based Health Care System for Elderly People

Worldwide Auto-mobi: Arduino IoT Home Automation System for IR Devices


A Low Cost Automated Fluid Control Device using Smart Phone for Medical Application

Data Monitoring and Hardware Control for App Android by Bluetooth Communication for Laboratory Teaching in Electrical Engineering Courses

Design of Smart Neonatal Health Monitoring System using Sensor Mobile Cloud Computing

Mining Human Activity Patterns from Smart Home Big Data for Healthcare Applications

Real-time Traffic Light Recognition Based on Smart Phone Platforms

EMBEDDED IEEE Projects 2017

A Real Time Street Lighting Control System

A Two-level Traffic Light Control Strategy for Preventing Incident-Based Urban Traffic Congestion

A Unified Framework for Vehicle Rerouting and Traffic Light Control to Reduce Traffic Congestion

Automatic Detection of Red Light Running Using Vehicular Cameras

Body and Fall Detection System with Heart Rate Monitoring

Design and Implementation of Low Cost ECG Monitoring System for the Patient using Smart Device

Economic Feasibility Of Solar Powered Street Lighting System In Libya

Handover in Outdoor Visible Light Communication System

Intelligent Home Automation System using BitVoicer

LED Projection Module Enables a Vehicle to Communicate with Pedestrians and Other Vehicles

On Detecting Acceptable Air Contamination in Classrooms using Low Cost Sensors

Reverse Engineering the Communications Protocol of an RFID Public Transportation Card

RFID-Based Attendance Management System

Syncretic Use of Smart Meters for Power Quality Monitoring in Emerging Networks

Towards Intelligent Arabic Text-to-Speech Application for Disabled People

Tuning of a Stigmergy-based Traffic Light Controller as a Dynamic Optimization Problem

Wheel Therapy Chair: A smart system for disabled person with therapy facility

BIOMETRIC IEEE Projects 2017

Anti-theft Protection of Vehicle by GSM & GPS with Fingerprint Verification

Design and Implementation of a Fingerprint Based Lock System for Shared Access

Flexible Microdisplacement Sensor for Wearable/Implantable Biomedical Applications

Indoor Localization Framework with WiFi Fingerprinting

SecureHouse: A Home Security System Based on Smartphone Sensors

ROBOTICS IEEE Projects 2017

An Android Based Human Computer Interactive System with Motion Recognition and Voice Command Activation

Low-Cost, Real-Time Obstacle Avoidance for Mobile Robots

Mine Detecting Robot Prototyping

Mobile Quad-Controlled Wireless Robotic Arm

Robotic Testing of Mobile Apps for Truly Black-Box Automation

WIRELESS IEEE Project titles 2017

A Real-Time Flood Alert System for Parking Lots

A Smart Meter Design and Implementation Using ZigBee Based Wireless Sensor Network in Smart Grid

A Study of the Mesh Topology in a ZigBee Network for Home Automation Applications

Design and Implementation of Real Time Transformer Health Monitoring System Using GSM Technology

E-health Acquistion, Transmission &Monitoring System

Electrical Appliances Control Prototype by Using GSM Module and Arduino

Energy-Efficient Localization and Tracking of Mobile Devices in Wireless Sensor Networks

Improvement in Multiple Access Channel Allocation for Sensor Node Configuration Based on RFID Communication

Lightweight Mashup Middleware for Coal Mine Safety Monitoring and Control Automation

Microcontroller based Digital Meter with Alert System using GSM

Realisation of a Smart Plug device based on Wi-Fi technology for use in Home Automation systems

SRAM-Based Unique Chip Identifier Techniques

SRAM-Based Unique Chip Identifier Techniques


Integrated circuit (IC) identification using unclonable digital fingerprints facilitates the authentication of ICs, device tracking, and cryptographic functions. In this paper, we present two hardware methods exploiting the inherent processinduced mismatch of SRAM cells. The proposed circuits improve upon those previously published by reducing the number of bits that vary from trial to trial, and can be used at times other than just IC power-up. The proposed circuits and methods are compared with the previous power-up approach using the experimental results from a 90-nm test chip. The required SRAM array periphery circuit changes allow the use of standard foundry SRAM cells and do not impact the memory access time. The proposed architecture of this paper the area and power consumption are analysis using tanner tools.



Change the technology based on the power reduction



Nonvolatile Memory Hardware Chip Identification

The most frequently used method of device authentication relies on programming an ID or a digital signature in a nonvolatile (NV) memory block, such as fuses, electrically erasable programmable read-only memory (EEPROM), or flash. NV ID memory has the advantage that the fingerprint is not lost when the device is powered OFF, but the cost of having an NV memory both in terms of area and process added cost precludes this approach in some markets.

Identification Using Physical Unclonable Functions

Another method of generating unique fingerprints is to utilize the inherent process variations in devices to create physically unclonable functions (PUFs). Random variations affect circuit properties, and by constructing the circuits sensitive to those properties, their behavioral differences can be utilized as IC IDs. PUFs using wire delays, gate delays, and ring oscillator frequencies have been proposed. The transistor threshold voltage (VT ) is directly dependent on random dopant fluctuations (RDFs), and is truly random, and thus ideally suited for PUFs. Su et al. proposed a VT mismatch-based identification method using crosscoupled NOR cells. Since RDF is the predominant cause of SRAM mismatch in mature processes, relying on VT strongly suggests using SRAMs for this function.

SRAM Power-Up State as an IC Identifier

SRAM is pervasive on modern ICs. The idea of using existing SRAM states during power-up as a fingerprint of the IC dates back to 2002 and has thoroughly been studied. Commercial SRAMs were powered up numerous times to calculate a statistically repeatable known-ID that was then used to authenticate any other fingerprints generated from further power-ups. Unfortunately, for embedded use, this scheme suffers from the drawbacks that include lack of support for ICs with built-in self-test (BIST) and that the resulting nonmatching codes may have considerably less than ideal code separation. BIST is required in many designs to set redundancy at power-up, which means that the SRAM state will not be random when available to software or hardware normal usage. In addition, the power-up SRAM cell state is influenced by process variations internal to the cell but importantly, by external noise. As the SRAM array is powered up, cells operate in the subthreshold region where they are most easily influenced by noise, potentially producing different power-up states up in different trials.


  • Power consumption is high


SRAM power-up state was extensively studied as a PUF. All SRAM cells have built-in mismatch due to as-fabricated process variations. The SRAM cell is a crosscoupled inverter pair with a built-in voltage offset (VOFFSET) due to RDFs, i.e., threshold voltage (VT) and other transistor, as well as node capacitance mismatches. Under normal conditions, the SRAM cell’s internal nodes, D and Q, shown in Fig. 2(a), are in one of two stable states DQ = 01 or DQ = 10. States DQ = 11 and 00 are unstable and thus unreachable in the normal operation. When the circuit is powered down (VDD = 0 V), the nodes D and Q are in the unstable 00 state.

Fig. 1. (a) Part of the test SRAM showing the decoder and SRAM array with different power supply voltages used to generate the IDs. Note that the circuit becomes identical to the traditional 6-T structure when VDDARRAY = VDD. (b) Write circuit to implement the BL_Low method. In normal operation, the ID_enable signal is deasserted and the data and its inverse appear on BL and BLN. However, when the ID_enable signal is asserted, both BL and BLN are forced toward VSS.

Proposed Methods and Principle of Operation

In contrast to using power-up, in both the methods proposed here, we force the SRAM into a metastable state (DQ = 11 or DQ = 00), with VDD applied to the SRAM cells. Thus, the SRAM state can be checked at times other than power-up, for instance, after BIST or as requested by a software application.

Fig. 2. (a) BL_High method drives current primarily through the nMOS access and pull-down devices NA0–N0 and NA1–NA1, respectively. (b) SRAM cell internal node (D and Q) waveforms applying the proposed method with both BLs driven to 1 V—BL voltages below show that the BLs cannot reach 1 V due to the strong nMOS pull-down transistors inside the cell. The WL is driven to a higher voltage (1.5 V here) to destabilize the cell and to 1 V, the nominal VDD (1 V here) to read out the value.

The overall operation of a word of SRAM as a PUF is similar to a sense amplifier, whereby the small voltage difference due to VOFFSET is amplified when the cross-coupled inverters are freed after the SRAM cell is driven to a metastable state. To force the nodes D and Q into the metastable state close to 11, the cell must be destabilized. To accomplish this, the access nMOS transistors are strengthened with respect to the pull-down transistors. This is accomplished by altering the voltages at the array level. Thus, the access transistors are made stronger than the pull-down nMOS transistors by increasing their gate overdrive, i.e., setting the word-line (WL) voltage VWL above the array supply voltage VDDARRAY when the fingerprint is taken [see Fig. 1(a)].

Method BL_High (BLs = 1)

For normal applications, the SRAM is read or written by driving the SRAM row WL to VDD = VDDARRAY. To implement the BL_High method, the timing and control circuits are modified to allow the BLs to be precharged, while VWL = VDD > VDDARRAY destabilizes the cell.

Method BL_Low (BLs = 0)

In this proposed method, the BLs are driven toward 0 V by simultaneously writing a logic 0 to each BL. In this scheme, the dominant ratio is that between the pull-up pMOS and the access nMOS transistors, e.g., P0 and NA0, respectively, as shown in Fig. 3(a). In this proposed method, the SRAM cell internal nodes are forced to metastable voltages close, but slightly greater than the 00 power-up point. The SRAM cell is easily destabilized even without the higher voltage on the WL. Therefore, the greater than VDDARRAY VWL voltage is not required.

Fig. 3. (a) BL_Low method drives current primarily through the nMOS access and pull-up pMOS devices NA0 from P0 and NA1 from P1, respectively. (b) Waveforms applying the proposed method with both BLs = 0 V—when driven metastable, the BLs near 0 V, since the pMOS transistors must be weak to ensure normal write-ability.

Circuit Operation

Although in both methods, the SRAM cell is forced to a metastable state, the bit-line voltage amplitude plays a significant role in determining the mismatch in the internal nodes’ VD − VQ (offset) voltage. The SRAM circuits in Figs. 2(a) and 3(a) illustrate the primary current flow through the access transistor NA0 and NA1 that creates the different voltages at nodes D and Q under different BL conditions, projecting the mismatch onto the SRAM cell logical state when the WL is deasserted.


  • Power consumption is reduced


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An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers

An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers



An add-on type real-time jitter tolerance enhancer (JTE) is presented in this paper. The proposed JTE can improve high-frequency jitter tolerance (JTOL) by using a real-time phase alignment scheme. A mathematical analysis for an advanced bit error rate (BER) prediction method is also introduced. The proposed circuit is applicable to various types of receivers, such as referenceless receivers, receivers with a reference clock source, and source-synchronous receivers. The referenceless receiver with the proposed JTE achieved an out-of-band JTOL of 0.71 UIpp at 100 MHz with < 10−12 BER. Total core areas of the receiver and JTE are 0.19 and 0.07 mm2 in a 0.13-µm CMOS process, respectively. The power consumption of the receiver is 38 mW at 5.4 Gbit/s, and the JTE dissipates 22 mW. The proposed architecture of this paper the area and power consumption are analysis using tanner tools.


Several JTOL-enhancing techniques have been reported in the literature. A gated-digital-controlled oscillator (GDCO)-based clock and data recovery (CDR) circuit were used to enhance JTOL by cascading the high frequency and low-frequency jitter tracking bandwidth (JTB) loops. The semi blind oversampling CDR uses the elastic FIFO to enhance the low-frequency JTOL. A clock-forwarded receiver with injection-locked oscillator (ILO) enhances the JTOL by increasing the JTB. However, the GDCO-based CDR requires an additional frequency calibration circuit in order to minimize its inherent frequency offset. Both the oversampling method and the FIFO incur a large power penalty and the very wide JTB increases unwanted clock jitter. The ILO also requires an additional frequency calibration circuit and a considerably high JTB makes the receiver vulnerable to the noise. Moreover, previous architectures presented in deal with methods to track the input data.



  • Jitter is produced



The overall architecture of the receiver with the proposed JTE is shown in Fig. 1. The receiver is composed of an equalizer (EQ), CDR [10], and JTE. The EQ employs an established EQ filter and compensates for the ISI of the input data. The CDR receives the EQ’s output, EQ_OUT, through the 4 delay line. These delay cells help to align the CLKALIGN at the center of the JTE’s delay line, so that the JTE can realign the input data with the maximum alignment range. The CDR operates as follows. First, the frequency detector sets up the VCO’s operating frequency with a random data pattern. Second, the phase detector and charge pump (CP) align CLKSAMPLING to the center of the 4-delayed EQ_OUT. Finally, the recovered clocks (CLK_OUT, CLKSAMPLING, and CLKALIGN) generated by the VCO, and EQ_OUT, are delivered to the JTE. The CDR shown in Fig. 1 is a reference for the JTOL performance comparison.

Fig. 1. Overall block diagram of the receiver with the proposed JTE.

The bottom of Fig. 1 shows a block diagram of the proposed JTE. Unlike the feedback architecture of the phase-aligner.

Equalizer and Delay Line

Fig. 2 shows a detailed block diagram of the EQ and the delay line. The EQ is composed of a continuous time linear EQ (CTLE), limiter, and current mode logic (CML)- to-CMOS converter, as shown in Fig. 2(a). The CML-toCMOS converter output, EQ_OUT, is a full swing signal, which means the JTE is insensitive to the input swing level. However, if the channel loss is too high to maintain the full swing, then the uncompensated ISI jitter from the EQ will be directly inserted to the JTE. In other words, if there are some residual ISI not cancelled by the CTLE, then that ISI will appear at the delay line output and it can be amplified at the worst corner.

Fig. 2. Block diagram of (a) EQ, (b) one delay cell, and (c) schematic of one inverter cell.

Edge Detector

Fig. 3 shows a block diagram of the proposed edge detector (ED). The ED consists of a dual-edge-triggered flip-flop (dual FF), XOR gates, and a selection code holder (SCH).

Fig. 3. Block diagram of the proposed ED.

Phase Selector

After the ED produces the selection code, the phase selector (PS) selects the multiphase data (2Δ, 4 Δ, and 6 Δ). A block diagram of the PS is shown in Fig. 4.

Fig. 4. Block diagram of the PS.



  • reducing the data jitter



  • Tanner tools

Dual-Calibration Technique for Improving Static Linearity of Thermometer DACs for I/O

Dual-Calibration Technique for Improving Static Linearity of Thermometer DACs for I/O


In this paper, we propose a dual-calibration technique to improve the matching accuracy of digital-to-analog converter (DAC) elements and improve nonlinearity induced static errors in a current-steering thermometer DAC. The novelty of the proposed dual-calibration scheme lies in obtaining best samples from the error distribution using redundancy for improved matching followed by adaptively reordering these samples to reduce error accumulation. This technique exploits the 2-D nature of the DAC to achieve lower calibration time. We consider the statistical basis for each of these methods and demonstrate statistical modeling of the proposed technique. We demonstrate a 38% reduction in differential nonlinearity (DNL) and 55% reduction in integral nonlinearity (INL) through simulations. We fabricated an 8-bit current steering thermometer DAC in Taiwan Semiconductor Manufacturing Company 65-nm CMOS process. With only 2 redundant cells per row, we show an improvement of 36% in DNL and 50% in INL from the measurement of 16 chips over the baseline DAC. The proposed architecture of this paper the area and power consumption are analysis using tanner tools.



Change the technology based on the error reduction.



As transistor sizes decrease with the scaling of CMOS processes, the area of a DAC’s unit cell and the overall DAC area also decrease. However, for a given process, matching accuracy among the unit cells is inversely proportional to area. This implies that unit cells need to be made larger to overcome the detrimental effect of increased nonlinearity and to maintain yield. Various preprocessing techniques such as special layout implementations, and biasing and routing schemes have been used to compensate for this loss in accuracy without growing the unit cells. These approaches are good for removing systematic geometric errors. However, they are not able to eliminate random mismatch errors that are becoming dominant in lower feature sizes. Hence, calibration becomes essential.

Calibration schemes for thermometer DACs fall mainly into two categories—trimming and switching. Trimming-based calibration methods focus on decreasing the mismatch error by calibrating each current source to a reference current using a calibration DAC. The issue with most of these schemes is the large amount of area added to the unit cells in the form of additional circuitry that does not scale well with process. Switching-based calibration methods focus on minimizing error accumulation by achieving mismatch error cancellation with successive addressing. Methods like dynamic element matching, which also increases the noise floor, and dynamic mismatch mapping, target dynamic linearity and do not reduce the overall power of the mismatch error that is important for improving the static linearity. Many other switching schemes use complex optimization algorithms requiring higher calibration time and power. In addition, no significant reduction in the mismatch error itself is achieved by the existing switching-based techniques.


  • Mismatch between the DAC’s unit elements



Fig. 1. Complete 8-bit dual-calibrated thermometer DAC architecture with all the calibration blocks and modified unit cell (shaded blocks used only during calibration).

The complete dual-calibrated DAC architecture is shown in Fig. 1. The calibration proceeds as follows. First, determine the median using the median detection block. Second, find the outliers in each row by first converting the analog current values from each cell and the median current to digital words. Next, calculate the absolute difference between the median value and the unit cell values and denote the two cells per row with the maximum absolute difference as the outliers. Following the outlier determination process, convert the summed row currents of the outlier-free DAC into digital words.

Median Detection

To determine the median current, we estimate the median value by comparing the current from the median cell (Fig. 2) with the current from each of the unit cells. The median cell is tuned to an output current such that the number of DAC unit cells with currents higher than the median cell’s is equal to the number of DAC unit cells with lower currents.

Fig. 2. Median detection circuit

Analog-to-Digital Conversion

Fig. 3. CSRO-ADC.

For both the methods involved in the dual-calibration technique, we convert the analog current values into digital words and then calculate the difference from the median and the ranking of rows in digital domain as it is done in many of the switching-based calibration techniques. Low-resolution analog-to-digital conversion is performed using a 6-bit current starved ring oscillator-analog-to-digital converter (CSRO-ADC), as shown in Fig. 3.

Design of DAC Unit Cell

Once the outliers for each row of the DAC have been determined, this information is stored in the unit cells as a valid bit (VB). The proposed DAC cell is similar to a standard single-ended DAC cell except for the additional memory to store the VB, as shown in Fig. 8. The memory is a standard 6T static random access memory (SRAM), along with a separate readout switch.

Fig. 4. (a) Column selection decoder. (b) Row selection decoder

Column Selection Decoder

The column decoder maps the column bits of the DAC via a binary-to-thermometer decoder, as shown in Fig. 4(a). Because of the redundant and invalid cells, the decoder also must consider the status stored in the memories of the cells in a row. If a cell is invalid, then it must be skipped by the decoder.

Row Selection Decoder

Due to the reordering of the rows, instead of a standard binary-to-thermometer decoder, a row selection decoder is used that consists of digital comparators and a memory bank of 16 4-bit SRAMs, where once the ranks of the rows have been determined, the order is stored. Each row rank is written sequentially, requiring 16 address cycles for this operation. For each row in the DAC, row selection decoder has two outputs—next Row and Row. During the DAC operation, the incoming row bits, rb are compared with the stored ranks using digital comparators, as shown in Fig. 4(b), to switch on the appropriate rows. For rows with rank > rb, Next Row is high and for rows with rank ≥ rb, Row is set high.


  • Improve the static linearity
  • Reduce the error


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Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization

Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization


Ultralow-power subthreshold logic circuits are becoming prominent in embedded applications with limited energy budgets. Minimum energy consumption of digital logic circuits can be obtained by operating in the subthreshold regime. However, in this regime process variations can result in up to an order of magnitude variations in ION/IOFF ratios leading to timing errors, which can have a destructive effect on the functionality of the subthreshold circuits. These timing errors become more frequent in scaled technology nodes where process variations are highly prevalent. Therefore, mechanisms to mitigate these timing errors while minimizing the energy consumption are required. In this paper, we propose a tunable adaptive feedback equalizer circuit that can be used with a sequential digital logic to mitigate the process variation effects and reduce the dominant leakage energy component in the subthreshold digital logic circuits. We also present detailed energy-performance models of the adaptive feedback equalizer circuit. As part of the modeling approach, we also develop an analytical methodology to estimate the equivalent resistance of MOSFET devices in subthreshold regime. For a 64-bit adder designed in 130 nm, our proposed approach can reduce the normalized variation of the critical path delay from 16.1% to 11.4% while reducing the energy-delay product by 25.83% at minimum energy supply voltage. The proposed architecture of this paper the area and power consumption are analysis using tanner tools.

PROJECT OUTPUT VIDEO: (Click the below link to see the project output video):


Use different combinational circuits.


Combinational logic refers to circuits whose output is strictly depended on the present value of the inputs. As soon as inputs are changed, the information about the previous inputs is lost, that is, combinational logics circuits have no memory. In many applications, information regarding input values at a certain instant of time is required at some future time. Although every digital system is likely to have combinational circuits, most systems encountered in practice also include memory elements, which require that the system be described in terms of sequential logic. Circuits whose outputs depend not only on the present input value but also the past input value are known as sequential logic circuits. The mathematical model of a sequential circuit is usually referred to as a sequential machine.

An edge-triggered flip-flop changes states either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock pulse on the control input. The three basic types are introduced here: S-R, J-K and D.

The S-R, J-K and D inputs are called synchronous inputs because data on these inputs are transferred to the flip-flop’s output only on the triggering edge of the clock pulse. On the other hand, the direct set (SET) and clear (CLR) inputs are called asynchronous inputs, as they are inputs that affect the state of the flip-flop independent of the clock. For the synchronous operations to work properly, these asynchronous inputs must both be kept LOW.

Subthreshold digital circuits suffer from the degraded ION/IOFF ratios resulting in a failure in providing rail-to-rail output swings when restricted by aggressive timing constraints. These degraded ION/IOFF ratios and process-related variations make subthreshold circuits highly susceptible to timing errors that can further lead to complete system failures. Since the standard deviation of VT varies inversely with the square root of the channel area, one approach to overcome the process variation is to upsize the transistors. Alternately, one can increase the logic path depth to leverage the statistical averaging of the delay across gates to overcome process variations. These approaches, however, increase the transistor parasitics, which in turn increases the energy consumption. In this paper, we first propose the use of a feedback equalizer circuit for lowering the energy consumption of digital logic operating in the subthreshold region while achieving robustness equivalent to that provided. Here, the feedback equalizer circuit (placed just before the flip-flop) adjusts the switching threshold of its inverter based on the output of the flip-flop in the previous cycle to reduce the charging/discharging time of the flip-flop’s input capacitance. Moreover, the smaller input capacitance of the feedback equalizer reduces the switching time of the last gate in the combinational logic block. Overall, this reduces the total delay of the sequential logic, which makes it more robust to timing errors and allows aggressive clocking to reduce the dominant leakage energy. In addition to reducing energy consumption, we also demonstrate how the tuning capability of the equalizer can be used to enable extra charging/discharging paths for the flip-flop input capacitance after fabrication to mitigate timing errors resulting from worse than expected process variations in the subthreshold digital logic.


  • Energy efficiency is less
  • Transition time is high


Fig. 1. Adaptive feedback equalizer circuit with multiple feedback paths (designed using a variable threshold inverter ) can be combined with a traditional master–slave flip-flop to design an adaptive E-flip-flop.

We first explain the use of the adaptive feedback equalizer circuit in the design of an adaptive equalized flip-flop (E-flip-flop) and then provide a detailed comparison of the E-flip-flop with the conventional flip-flop in terms of area, setup time, and performance. We propose the use of a variable threshold inverter (Fig. 1) as an adaptive feedback equalizer along with the classic master–slave positive edge-triggered flip-flop (Fig. 2) to design an adaptive E-flip-flop. This adaptive feedback equalizer circuit consists of two feedforward transistors (M1 and M2 in Fig. 1) and four control transistors (M3 and M4 for feedback path 1 that is always ON and M5 and M6 for feedback path 2 that can be conditionally switched ON postfabrication in Fig. 1) that provide extra pull-up/pull-down paths in addition to the pull-up/pull-down path in the static inverter for the Data FlipFlop input capacitance.

Fig. 2. Circuit diagram of classic master–slave positive edge-triggered flip-flop

e analyze the capability of the adaptive feedback equalizer circuit to reduce the transition time of the last gate in critical path of the subthreshold logic and make a comparison with the original nonequalized design, and the buffer-inserted nonequalized design (Fig. 3). The classic buffer insertion technique [Fig. 3(c)] will reduce the total delay along critical path of the subthreshold logic. Like the gates in the combinational logic, the buffer used in Fig. 3(c) is upsized to account for the process variation effects based on the design methodology proposed.

Fig. 3. Block diagrams of (a) original nonequalized design, (b) equalized design with one feedback path ON, and (c) buffer-inserted nonequalized design.


We present detailed AMs for the performance and the energy of adaptive equalizer circuits operating in the subthreshold regime. Using these models, we determine the sizes for feedforward transistors and control transistors in the feedback equalizer circuit that minimize total delay and leakage energy for the equalized subthreshold logic. Without loss of generality, we choose minimum-sized transistors for matching high-to-low and low-to-high propagation delay in the static inverter of the feedback equalizer circuit. As part of the effort, we first develop an analytical methodology to calculate the equivalent channel resistance of active MOSFET devices operating in the subthreshold regime. The proposed model is validated against HSPICE simulations (HSs) using UMC 130-nm process.


  • improve energy efficiency
  • mitigate process variation effects
  • transition time is reduced


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A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter with Cycle-Controlled DPWM

A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter with Cycle-Controlled DPWM


This paper presents a wide-voltage-range, fast-transient all-digital buck converter using a high-resolution digital pulsewidth modulator (DPWM). The converter employs the multithreshold-voltage band-control technique to shorten its transient response. The DPWM uses an all-digital delay-locked loop (ADDLL) to control its cycle. The usage of ADDLL leads to the DPWM possessing a small area while maintaining high cycle resolution. Moreover, the proposed ADDLL-based cycle controlled DPWM can achieve synchronization between its input and output. This decreases the loop delay of the proposed converter so that the system is easy to be stabilized. The prototype chips of both the ADDLL-based cycle-controlled DPWM and the all-digital buck converter are fabricated in 0.35-µm CMOS process. Measurement results of the cycle controlled DPWM show that the duty cycle of its output is adjustable from 1% to 99% in a 0.78% increment per step when operating at 1 MHz. The measured transition time of the all-digital buck converter is < 3.5 µs when the load current changes from 50 to 500 mA, and vice versa. The proposed architecture of this paper the area and power consumption are analysis using tanner tools.

PROJECT OUTPUT VIDEO: (Click the below link to see the project output video):


A conventional buck converter is realized in analog circuits, and it requires lots of passive components in its compensator to stabilize the loop. Compared with the analog realizations, the digital buck converters are not only less sensitive to the process, voltage, and temperature (PVT) variations but also much easier to be integrated into a system-on-a-chip solution. Furthermore, benefiting from the digital nature, it is much easier for engineers to design process independent all-digital buck converters than to design their analog counterparts. All the above features make the all-digital buck converters attractive in power management applications.

Fig. 1 shows the conventional digital-controlled buck converter. It consists of an analog-to-digital converter (ADC), a digital compensator, a digital pulsewidth modulator (DPWM), two power transistors, and an LC output filter. Conventionally, the digital-controlled buck converters are not popular in power management because of the following reasons.

Fig. 1. Conventional digital-controlled buck converters.

  1. The high-resolution ADC in a buck converter consumes significant power and occupies a large chip area. Meanwhile, an ADC is extremely sensitive to the supply voltage variation. Furthermore, designing a high-resolution ADC takes intensive design efforts.
  2. The digital compensator is usually realized by a lookup table circuit, which also occupies a large chip area.
  3. To realize a high-resolution DPWM, lots of delay elements and multiplexers (MUXs) are required. This results in a considerable increase of the chip area. On the other hand, the latencies for generating different duty-cycle outputs are different. It is difficult to keep the buck converter stable for such a wide range of latency.
  4. Limit cycle oscillations (LCOs) due to finite precision of the ADC and/or finite precision of the DPWM may occur in the digital-controlled buck converter. This not only worsens the ripples in its regulated output, but also limits the tunable output range of the buck converter.
  5. The response time of the digital-controlled buck converter highly depends on the operating frequency of the digital controller and the converter itself. To fulfill the fast-transient requirement for a load change, the operating frequency of the digital controller and the converter itself should be as high as possible. Unfortunately, increasing the operating frequency of the converter worsens the switching loss dramatically and lowers the converter’s conversion efficiency.


  • Duty cycle range is less
  • Power management is not better


Fig. 2. Simplified architecture of the fast-transient wide-voltage-range, all-digital buck converter.

Fig. 2 shows the simplified architecture of the proposed fast transient all-digital buck converter. It consists of two power transistors, a MUX, a linear control circuit, a MTVB control circuit, a divider, a lock detector (LD), a dead-time circuit with buffers, and an LC output filter. Two clock signals, CLK and CLK Div, are used for the linear control circuit to lower the power consumption. To shorten the response time of the buck converter, the feedback control of the proposed buck converter operates in two modes, the nonlinear control mode and the linear control mode, according to the outputs of the MTVB control circuits. If the regulated output is outside the voltage range delimited by [VL, VH], the buck converter operates in the nonlinear control mode by selecting the comparison result of the MTVB control circuit (Comp) through the MUX to modulate the power transistor.

Fig. 3. Flowchart of the proposed all-digital buck converter

Fig. 3 shows the flowchart of the control mechanism of the proposed buck converter. The linear control mechanism of the proposed all-digital buck converter employs the pulse width modulation (PWM) due to its high conversion efficiency during the heavy-load period in which the PWM controller introduces smaller ripples to the regulated output than any other control technique does.

Fig. 4. Block diagram of the linear control circuit.

Fig. 4 shows the block diagram of the linear control circuit. It consists of a 7-bit up/down counter, a cycle-controlled DPWM, and a three-input AND gate. To reduce the power consumption in the up/down counter, the operating frequency of the counter is chosen lower than the operating frequency of the DPWM. The duty cycle of the cycle-controlled DPWMs output is adjustable depending on the logic level of Comp at every rising edge of CLK. If Comp is logic HIGH, the output duty cycle of the DPWM increases. Otherwise, the output duty cycle of the DPWM decreases.

MTVB Control Circuit

Fig. 5. Schematic of the MTVB control circuit and its truth table.

Fig. 5 shows the schematic of the MTVB control circuit and its truth table. It consists of three hysteresis comparators and one NAND gate. The hysteresis comparators are utilized here to prevent the comparison results from being affected by the unexpected high-frequency spikes of Vout. The first comparator, Comp1, compares the regulated output, Vout, with the target voltage, VRef, and generates a binary output, Comp. The second and the third comparators, Comp2 and Comp3, are used to detect whether VH > Vout > VL or not.

Cycle-Controlled DPWM

Fig. 6(a) shows the simplified architecture of the DPWM. A pulse generator is utilized to generate a fixed duty cycle output, CLKPULSE. This prevents both inputs of the NOR-based set-reset flipflop (SRFF) from being set to logic HIGH at the same time. The rising edge of CLKPULSE sets the SRFF to logic HIGH. Meanwhile, CLKPULSE also enters the cycle-controlled delay line (CCDL). After passing through the delay line, the rising edge of its delayed version, CLKR, resets the SRFF to logic LOW. The schematic of the CCDL and its timing diagram are shown in Fig. 6(b). It consists of an MUX, a deMUX (DEMUX), a one-shot circuit, a digital-controlled delay line (DCDL), an inverter, a 7-bit counter, and a 7-bit comparator.

Fig. 6. (a) Simplified architecture of the DPWM. (b) Schematic of the CCDL and its timing diagram.

Fig. 7 shows the detail schematic of the cycle-controlled DPWM and its corresponding timing diagram. The proposed cyclecontrolled DPWM consists of a start-controlled circuit [17], one pulse generator [18], a MUX, a DEMUX, a DCDL [19], a 7-bit counter, a 7-bit successive-approximationregister (SAR) circuit [20], a bit comparator, an SRFF, a DFF, a phase detector (PD), and some control logics as shown in Fig. 7(a). The proposed DPWM has two operation modes, namely, the ADDLL mode and the DPWM mode, respectively. The timing diagram of the DPWM is shown in Fig. 7(b).

Fig. 7. (a) Proposed cycle-controlled DPWM. (b) Timing diagram of the cycle-controlled DPWM.

Lock Detector

To avoid dithering of the comparison results between VRef and Vout due to the finite resolution of digital circuits, an LD is employed to detect dithering of Comp, the comparison result of the MTVB circuit.


  • wide duty cycle control
  • regulated output’s tunable range wide


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Design of a CMOS System-on-Chip for Passive, Near-Field Ultrasonic Energy Harvesting and Back-Telemetry

Design of a CMOS System-on-Chip for Passive, Near-Field Ultrasonic Energy Harvesting and Back-Telemetry


Many packaging and structural materials are made of conductive materials such as metal or carbon-fiber composites, which limits the use of embedded radio frequency-based telemetry systems for sensing. In this paper, we present the design of a complete passive ultrasonic energy harvesting and back-telemetry system that exploits near-field acoustic coupling to wirelessly transfer energy and data across conductive barriers. The use of near-field operation makes the telemetry robust to multipath reflections that occur at barrier discontinuities and robust to crosstalk when multiple sensors are simultaneously interrogated. Underlying the proposed architecture is a systemon-chip (SoC) that integrates different ultrasonic energy harvesting and telemetry modules. The operation of the system has been verified using SoC prototypes fabricated in a 0.5-µm CMOS process which have been integrated with a piezoelectric transducer attached to an aerospace-grade aluminum substrate. Measured results show that the proposed near-field ultrasonic telemetry system can effectively operate across a 2-mm-thick metallic barrier at a frequency of 13.56 MHz with the SoC consuming 22.3 µW of power. The proposed architecture of this paper the area and power consumption are analysis using tanner tools.


Chance the parameter and technology


An alternative to RF-based telemetry is acoustic- or ultrasonic-based telemetry, which has been demonstrated to exhibit low attenuation inside conductive media. The use of ultrasound allows miniaturization of the embedded telemetry system by relaxing the size requirements on the piezoelectric transducer (PZT). In addition, unlike RF transmission, which is regulated according to FCC requirements, ultrasonic power delivery and transmission, is only limited by the structure’s mechanical compliance. In literature, several ultrasonic telemetry systems have been reported for use in metallic structures and for in vivo applications. Passive ultrasonic telemetry systems have also been reported that eliminate the need for batteries on the sensors. However, all these systems are either bulky or power hungry, and thus are not suitable for massive deployment in practical applications.


  • Area coverage and Power consumption is high


The system architecture of a ultrasonic back-telemetry system is shown in Fig. 1. The reader comprises the digital controller, the analog front-end (AFE) and the impedance matching circuit. The digital controller implements a state machine that sends and receives commands to and from the tag. The AFE modulates the digital signal with ultrasonic carrier and demodulates the backscatter signal. The impedance matching circuit is used to create a resonant network comprising the transmit PZT, the transmission medium and the receive tag.

Fig. 1. Proposed ultrasonic communication system.

The receiver tag consists of a receive PZT and a matching circuit which forms a part of the ultrasonic resonant network. Through this network, the tag receives electrical power and a power management module comprising of voltage multipliers and voltage regulators generate stable supply voltages for other on-chip modules. A demodulator extracts the raw data received over the resonant network and a digital state-machine performs error-correction and decodes the commands received from the reader.

Power Management Circuits

Due to the attenuation of the ultrasonic signal inside the solid medium and the transducer’s limited energy conversion efficiency as well as the impedance mismatch at various interface, the magnitude of the signal induced at the receive PZT is typically capacitor. For this implementation we have used a standard Dickson type multiplier, as shown in Fig. 2. The multiplier comprises of Schottky junction diodes (with approximate threshold voltage of Vth ≈ 300 mV) and produces an output voltage VOUT ≈ N · (VIN − Vth), with N being the number of multiplier stages.

Fig. 2. Power management modules, which include a voltage multiplier, a voltage limiter, and a regulator

Data Recovery Circuit

The data recovery circuit is shown in Fig. 3(a) and demodulates a pulse-interval encoded (PIE) modulation signal. In a PIE code, a long duration between two digital pulses represents logic 1, and a short duration between two pulses represents logic 0. The envelope of the modulated piezoelectric signal is first extracted by a voltage doubler followed by a low-pass filter. A comparator then compares the filtered signal with V2, which is the midpoint of the supply voltage. Since the dc component of the V1 equals V2, the comparator extracts the PIE signal.

Fig. 3. (a) Block diagram. (b) Detailed circuit design of data recovery circuit.

Digital Baseband and Manchester Encoder

The digital baseband module includes the preamble circuit, the ADC controller, and the Manchester encoder. The PIE data transmitted from the reader to the tag are encapsulated in a frame consisting 4-bit preamble bits, 3-bit command bits, and a 1-bit CRC code, as shown in Fig. 4(a).

Fig. 4. Communication protocol. (a) PIE. (b) Manchester.

Sensor Data Acquisition Circuitry

A POR detects the change in the supply voltage and generates a delayed digital pulse, which is used to initialize all the digital logic and internal registers. The delay time td is determined by the charging current Ich and capacitor size Cc

td = (CcVth)/ Ich                                   (1)

where Vth is the threshold of the inverter. In addition, the current-starved inverters have been used to minimize the power dissipation.


  • Area and power is reduced


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PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices

PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices


Evaluation of novel devices in the context of circuits is crucial to identifying and maximizing their value. We propose a new framework, Pareto optimization-based circuit-level evaluator for emerging device (PROCEED), that uses comprehensive performance, power, and area metrics for accurate device-circuit coevaluation through optimization of digital circuit benchmarks. The PROCEED assesses technology suitability over a wide operating region (megahertz to gigahertz) by leveraging available circuit knobs (threshold voltage assignment, power management, sizing, and so on). It improves the benchmark accuracy by 3× to 115× compared with the existing methods while offering orders of magnitude improvements in runtime over full physical design implementation flows. To illustrate the PROCEED’s capabilities, we deploy it to assess emerging technologies, including novel tunneling field-effect transistors, compared with conventional silicon CMOS. As a further illustration, we extend PROCEED to evaluate future heterogeneous integration of varied devices onto the same silicon substrate. The proposed architecture of this paper the area and power consumption are analysis using tanner tools.


Device-circuit assessments must consider several factors to draw realistic conclusions. First of all, any effective power and delay evaluation of modern circuits should cover several orders of magnitude, since their operating frequencies range from kilohertz to gigahertz. Second, chip area, ignored in all current evaluation methods, should be simultaneously considered because of its impact on manufacturing cost and interconnect length. Third, the crucial tuning knobs, such as logic gate sizing and supply voltage (Vdd) or threshold voltage (Vt) selection, must be optimized for proper use of a particular circuit. Fourth, since circuit performance depends critically on the device operating point, benchmarks should consider the full device current–voltage (I–V) characteristics rather than only simplified metrics such as saturation current (ION) or OFF-state leakage (IOFF). Fifth, a given device may not be suitable for all circuit architectures because of variations in logic depth histogram (LDH) patterns, and logical or physical structure. Sixth, as technologies scale down, device variability due to ambient process fluctuations becomes ever more important and impacts circuit viability. Seventh, the benefits to circuit designs of cooperatively using several device types through heterogeneous integration (HGI) are strongly dependent on the design adaptability and circuit topology, which must be considered in any assessment. All the aforementioned complexities would mandate a complete circuit design flow for performance evaluation, which is nevertheless impractically time-consuming. Therefore, an alternative evaluation method must be developed that accounts for the above factors with reasonable computational run time.


  • Delay power product and delay area product is high


Fig. 1. Overview of PROCEED framework

As shown in Fig. 1, typical inputs to PROCEED include interconnect information, such as average wire resistance (R) and capacitance (C) and chip size, circuit benchmark design (i.e., design LDH and average fan-out), variability (through Vdd drops, Vt shifts, and so on), full device I–V models, and operating activity, as well as optional constraints on Vdd, Vt , chip area, and the ratio of average to peak throughput (i.e., clock cycles per second).

Canonical Circuit Construction

A complete and exact optimization is an impossible job for large digital circuits. Since the goal of PROCEED is to predict the best performance and power tradeoffs for emerging devices, detailed circuit design is not our target and it contributes little to evaluation. We therefore use only essential design information to maximize performance and determine the optimal Vdd, Vt , and gate sizes for a given power consumption limit.

Fig. 2. (a) Example of simulation block allocation in PROCEED based on logic depth. (b) Circuit schematic used for simulation and optimization.

In Fig. 2, we show an example of the simulation blocks used to construct a specific circuit. For simplicity, we first dividelogic paths into n bins based on logic depth; in Fig. 2(a), for instance, n = 5. A larger number of bins improve accuracy at the expense of computation time. Each bin is modeled by corresponding simulation blocks Si [S1–S5 in Fig. 2(a)], which are in turn made of i gate stages. We use the gate design for Si to construct logic paths belonging to a given bin i.

The LDH is divided in such a way that the longest path in each bin has the same delay if all these blocks have the same delay. The logic gate and interconnect used for a single stage in the simulation blocks is shown in Fig. 2(b). The gate can be NAND, NOR, or something more complicated like XNOR, depending on the average number of transistors per gate in the chosen benchmark.

Delay and Power Modeling

Delay, power, and area are the three most important gross metrics in the design of digital circuits, but usage constraints lead to tradeoffs between them that must be balanced to maximize the overall efficiency of the design. Hence, we use them as evaluation metrics in PROCEED.

Area Modeling

The area of the gates used in canonical circuit constructions is simulated using UCLADRE1, where they are minimized in accordance with input design rules and gate netlists.

Fig. 3. (a) NAND gate. Schematic and layouts for (b) CMOS and (c) TFET

Fig. 3(a) shows a NAND gate logic schematic, where adjacent transistors share a source/drain at node n1. Fig. 3(b) stacks two nMOS devices to create a compact layout for traditional CMOS technology. However, due to the source/drain asymmetry, a TFET layout for the same circuit must split the stack, leading to additional area overhead, as shown in Fig. 3(c). To account for this effect, we modify UCLADRE such that it generates area-optimal TFET layouts for any input circuit netlist.


Fig. 4. Optimizer overview. Adaptive weight is chosen by slope of existing fronts. Based on starting point, metamodeling is built and gradient descent is used to find potential points. Simulate potential points to get new Pareto points.

PROCEED can simultaneously optimize any two metrics out of delay, power, and area, while the third is treated as a constraint; for instance, we can perform a Pareto optimization of delay and power with a maximum area constraint. As described in Section II-B, the chosen area model is linear in gate width and hence easier to optimize than delay and power. Therefore, in the remainder of this section, we will describe in detail the Pareto optimization of delay and power with constrained area. Fig. 4 shows an overview of our Pareto optimization process.


  • Delay power product and delay area product is reduced


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Power Efficient Level Shifter for 16 nm FinFET near Threshold Circuits

Power Efficient Level Shifter for 16 nm FinFET near Threshold Circuits


Since the minimum feature size has shrunk beyond the sub-30-nm node, power density has become the major factor in modern microprocessors. Techniques such as dynamic voltage scaling operating down to near threshold voltage levels and supporting multiple voltage domains have become necessary to reduce dynamic as well as static power. A key component of these techniques is a level shifter that serves different voltage domains. This level shifter must be high speed and power efficient. The proposed level shifter translates voltages ranging from 250 to 790 mV, and exhibits 42% shorter delay, 45% lower energy consumption, and 48% lower static power dissipation. In addition, the proposed level shifter exhibits symmetric rise and fall transition times with up to 12% skew at the extreme conditions over the maximum range of voltages. The proposed architecture of this paper the area and power consumption are analysis using tanner tools.



Change the nanometer technology based on the power and area reduction.



Level shifter circuits are typically based on one of three approaches. One approach is based on a differential cascade voltage switch (DCVS) level shifter. This approach is discussed in this section to exemplify the basic principles used by the proposed level shifter. A second approach uses a Wilson current mirror in the amplifying stage. The third approach utilizes a specialized circuit topology.

Standard Level Shifter

A standard level shifter topology is typically based on a DCVS gate . A DCVS level shifter circuit is shown in Fig. 1. The input NMOS transistors are controlled by a low voltage input signal, which is shifted to a high voltage at the output of the level shifter. The DCVS level shifter operates as follows. For the case when in=1 (e.g., 250 mV) andin=0(e.g.,0V),out=1 (e.g., 790 mV) and out =0 (e.g., 0 V). When the input transitions toin =0 (e.g., 0 V) andin=1 (e.g., 250 mV), the NR transistor enters theOFF state, while the NL transistor begins to conduct current, discharging nodeout. The gate of the PL PMOS transistor is, however, connected to node out, which remains at 0 V, maintaining PL on to resist the NL transistor by simultaneously charging node out. Note that the gate of NR and NL is connected to the low input signal.

Fig. 1. Standard level shifter based on simple DCVS gate.

These transistors operate near the cutoff region. The gate of PR and PL is connected to the high voltage supply. In this configuration, NL and NR struggle to sink more current than the PMOS pull-up transistors source. If NL sinks greater current than the PMOS pull-up transistor sources, node out discharges. The PR transistor toggles from the OFF state to the ON state, and charges node out (e.g., 790 mV), which cuts off the pull-up transistor PL, completing the transition.

Advanced Level Shifter

Additional logic is added to improve the performance and decrease the size of the NMOS pull-down transistors. The additional transistors are NRT, NLT, PRT, and PLT (Fig. 2). This circuit structure improves on the standard level shifter in two ways. First, the NMOS transistors NLT and NRT are biased at a nominal voltage (Vddh); NL and NR can, therefore, be smaller than a standard level shifter. NL and NR should, however, be sufficiently large to force the transition within the differential structure. When the differential input is sufficiently shifted, the significantly stronger NLT and NRT transistors complete the transition. Second, the PMOS transistors, PLT and PRT, are controlled with corresponding input voltage to limit the current flowing through the full voltage pull-up transistors, PL or PR. For high input in (in), PLT (PRT) is fully ON, providing the desired charging current, while PRT (PLT) limits the current, allowing the NR (NL) and NRT (NLT) NMOS pull-down network to discharge the out(out) node.

Fig. 2. Advanced level shifter based on DCVS gate with additional logic to improve speed


  • Less sensitivity
  • Delay is high
  • power efficiency is low



The proposed circuit dynamically changes the current sourced by the relevant PMOS pull-up transistor (PL/PR) to ensure that the weak NMOS pull-down transistor (NL/NR) sinks more current than the PMOS pull-up (PL/PR) network sources. The proposed low voltage level shifter is shown in Fig. 3.

Structure of the Proposed Wide Voltage Range Level Shifter The novelty of this circuit topology is the feedback loop. The feedback loop consists of a delay element that connects the output node D(high voltage domain) to the input of two multiplexers, MUXL and MUXR. The delay element is based on two minimum sized serially connected inverters. These inverters are supplied with a high voltage (790 mV) and receive a high voltage signal Das an input. This delay element does not affect the delay of the proposed level shifter, since the delay element is within the feedback loop that sets up the circuit for the next transition. The MUXs are based on two sets of pass gates, as shown in Fig. 4. The output of MUXL (high voltage domain) is connected to the gate of the PMOS pull-up transistor PL. When select is high (high voltage domain), the gate of PL is connected to the intermediate voltage Vddm, which temporarily weakens PL. When select is low, the gate of PL is connected to node D, which preserves the differential operation. Similarly, the output of MUXR is connected to the gate of the PMOS pull-up transistor PR. When select is high, the gate of PR is connected to node D, which preserves the differential operation. When select is low, the gate of PR is connected to the intermediate voltage Vddm, which temporarily weakens PR.

Structure of the proposed wide voltage range level shifter, including (a) level shifter circuit, (b) internal MUX structures, and (c) intermediate voltage generator.

This configuration eliminates the need for the large NMOS pull-down transistors, NLand NR, because the relevant PMOS pull-up transistor is maintained at a low voltage bias for the upcoming transition. This approach also greatly lowers the transition time as compared with other level shifters .

The intermediate voltage Vddm is generated by a voltage divider, as shown in Fig. 3, which consists of five minimum sized diode connected PMOS transistors. In this configuration, a stable bias voltage of 450 mV is generated to weaken, as needed, the pull-up PMOS transistors.



  • Increased sensitivity
  • Speed increased
  • Energy improved
  • power efficiency is increased



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Concept, Design, and Implementation of Reconfigurable CORDIC

Concept, Design, and Implementation of Reconfigurable CORDIC


This brief presents the key concept, design strategy, and implementation of reconfigurable coordinate rotation digital computer (CORDIC) architectures that can be configured to operate either for circular or for hyperbolic trajectories in rotation as well as vectoring-modes. It can, therefore, be used to perform all the functions of both circular and hyperbolic CORDIC. We propose three reconfigurable CORDIC designs: 1) a reconfigurable rotation-mode CORDIC that operates either for circular or for hyperbolic trajectory; 2) a reconfigurable vectoring-mode CORDIC for circular and hyperbolic trajectories; and 3) a generalized reconfigurable CORDIC that can operate in any of the modes for both circular and hyperbolic trajectories. The reconfigurable CORDIC can perform the computation of various trigonometric and exponential functions, logarithms, square-root, and so on of circular and hyperbolic CORDIC using either rotation-mode or vectoring-mode CORDIC in one single circuit. It can be used in digital synchronizers, graphics processors, scientific calculators, and so on. It offers substantial saving of area complexity over the conventional design for reconfigurable applications. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.

PROJECT OUTPUT VIDEO: (Click the below link to see the project output video):


The rotation-mode CORDIC determines the coordinates of any given vector after rotation through a given angle, while in the vectoring-mode it computes the magnitude and phase of the vector. The unified algorithm for linear and hyperbolic CORDICs is an extension of the basic CORDIC algorithm for circular trajectory. It is based on the generalized principle proposed to include hyperbolic and linear trajectories along with the original circular trajectory of operation. A variable m is introduced to modify the rotation matrix and elementary angles as

Where m = 1 for circular, m = 0 for linear, and m = −1 for hyperbolic trajectories, respectively. To guarantee the convergence in hyperbolic mode, the iterations i = 4, 13, 40,… need to be executed twice. It is shown that the scale-factor converges to a constant K = 1.2075 (0.60725) for hyperbolic (circular) trajectory. Consequently, we have different scale-factors for the circular and hyperbolic trajectories. The unified CORDIC algorithm supports a range of convergence (RoC) of [−99°, 99°] for circular trajectory, while the RoC for hyperbolic trajectory is |θ| ≤ 1.1182 radians (nearly 64°).

Realization of Vectoring-Mode CORDIC

In vectoring-mode, the phase and magnitude of any given vector are computed by aligning the vector along x-axis. This is achieved by performing microrotations in the direction, which drives the y-coordinate to zero. Equations (1) and (2) are extended to vectoring-mode by changing the control variable that determines the direction. In rotation-mode, the residual angle θi acts as the control variable for determining the direction of microrotations, while in vectoring-mode, the control variable is y-coordinate. If yi is positive, the direction of microrotation is clockwise, while it is anticlockwise if yi is negative.


  • Area coverage is high


To design a reconfigurable CORDIC architecture with minimum reconfiguration overhead, we need to maximize the sharing of common hardware circuit in different configurations. Therefore, to explore the possibility of reconfigurable CORDIC, we examine, here, the commonalities in three main issues of CORDIC implementation, namely:

  1. The coordinate-rotation matrix.
  2. Selection of elementary angles.
  3. Direction of micro rotations.

Reference Reconfigurable CORDIC

A basic design for reconfigurable CORDIC based on unified CORDIC algorithm was proposed. The major concern with the design of conventional reconfigurable architecture is the incompatibility in RoC of circular and hyperbolic trajectories. The RoC of circular CORDIC is [−99°, 99°], while that of hyperbolic CORDIC is given by |θ| ≤ 1.1182 radians. This limits the maximum angle of rotation of the reconfigurable design to 64°. The incompatible RoC of circular and hyperbolic CORDICs makes it difficult to implement them in the same circuit to perform rotation through [−180°, 180°].

Design Strategy for Proposed Reconfigurable CORDIC

As discussed in Reference Reconfigurable CORDIC, the circular and hyperbolic CORDICs require two different scaling circuits, which is quite costly. Therefore, it is necessary to use a scale-free implementation in the reconfigurable CORDIC. Here, we discuss the scaling-free CORDIC and its limitations, followed by the discussions on our design strategy for a reconfigurable CORDIC.


The coordinate calculation matrices for circular and hyperbolic CORDICs differ by the sign of operands, and to realize that additions are to be replaced by subtractions and vice-versa. This can be easily realized by a reconfigurable add/subtract circuit. In both cases, the basic-shift could be either 2 or 3, but the number of micro rotations varies with the mode of operation. Besides, each case will have its own circuit to enable the extension of RoC. Based on these observations, we design three reconfigurable CORDIC architectures:

  1. Rotation-mode reconfigurable CORDIC.
  2. Vectoring-mode reconfigurable CORDIC.
  3. Generalized reconfigurable CORDIC.
  1. A) Rotation-Mode Reconfigurable CORDIC

Fig. 1. Proposed reconfigurable rotation-mode CORDIC processor

The proposed design for reconfigurable rotation-mode CORDIC (shown in Fig. 1) consists of three parts:

  1. Preprocessing unit.
  2. Reconfigurable CORDIC rotation unit.
  3. Post processing unit.

Fig. 2. Structure of the proposed reconfigurable recursive CORDIC architectures.

  1. Proposed Recursive Architecture: The recursive architecture (shown in Fig. 2) uses a single CORDIC micro rotator to perform all the CORDIC iterations. The reconfigurable coordinate calculation unit (RCCU) is shown in Fig. 3.
  2. Fig. 3. RCCU for recursive design.
  3. Proposed Pipelined Architecture: Fig. 4 shows the reconfigurable CORDIC rotation unit for basic-shift 2. The shift-index si is fixed in every RCCU, and hence the shifters are hardwired and do not involve high complexity barrel-shifters. The implementation of RCCUs varies according to the basic-shift si. With slight modifications, the pipeline can be extended for basic-shift 3.
  4. Fig. 4. Reconfigurable rotation-mode CORDIC unit for basic-shift 2.
  1. Reconfigurable Vectoring-Mode CORDIC

By changing the implementation of the RCCU to implement (8), the recursive architecture of Fig. 2 can be used to realize CORDIC iterations for vectoring-mode. The rollover counter value is 15 for sbasic = 2, and 17 for sbasic = 3.

The pipelined architecture of vectoring-mode reconfigurable CORDIC consists of eight stages for sbasic = 2, as shown in Fig. 5. Similar to reconfigurable rotation-mode CORDIC, for increasing shift-indices, the implementation of RCCUs is simplified for reconfigurable vectoring-mode CORDIC as well.

Fig. 5. Proposed pipeline reconfigurable vectoring-mode CORDIC unit for sbasic = 2.

Proposed Generalized Reconfigurable CORDIC

The generalized reconfigurable CORDIC can operate either in vectoring-mode or in rotation-mode for both circular and hyperbolic trajectories. The user can select the trajectory of operation using a single bit signal T.

Fig. 6. Structure of CORDIC microrotator for the proposed recursive generalized reconfigurable CORDIC.

The recursive architecture of the proposed generalized reconfigurable CORDIC is implemented by combining the CORDIC microrotators for both rotation-mode and vectoring-mode CORDICs, as shown in Fig. 6. The throughput of the proposed recursive generalized reconfigurable CORDIC is the same as that of the recursive reconfigurable vectoring-mode CORDIC.

Fig. 7. Proposed pipeline generalized reconfigurable CORDIC unit for sbasic = 2.

The block diagram for pipelined generalized reconfigurable CORDIC using basic-shift sbasic = 2 is shown in Fig. 7. It can be easily extended to basic-shift sbasic = 3 as is done for reconfigurable rotation-mode and vectoring-mode CORDICs.


  • Reduce the area
  • maximum operating frequency


  • Modelsim
  • Xilinx ISE