SRAM-Based Unique Chip Identifier Techniques

SRAM-Based Unique Chip Identifier Techniques

ABSTRACT:

Integrated circuit (IC) identification using unclonable digital fingerprints facilitates the authentication of ICs, device tracking, and cryptographic functions. In this paper, we present two hardware methods exploiting the inherent processinduced mismatch of SRAM cells. The proposed circuits improve upon those previously published by reducing the number of bits that vary from trial to trial, and can be used at times other than just IC power-up. The proposed circuits and methods are compared with the previous power-up approach using the experimental results from a 90-nm test chip. The required SRAM array periphery circuit changes allow the use of standard foundry SRAM cells and do not impact the memory access time. The proposed architecture of this paper the area and power consumption are analysis using tanner tools.

 

ENHANCEMENT OF THE PROJECT:

Change the technology based on the power reduction

 

EXISTING SYSTEM:

Nonvolatile Memory Hardware Chip Identification

The most frequently used method of device authentication relies on programming an ID or a digital signature in a nonvolatile (NV) memory block, such as fuses, electrically erasable programmable read-only memory (EEPROM), or flash. NV ID memory has the advantage that the fingerprint is not lost when the device is powered OFF, but the cost of having an NV memory both in terms of area and process added cost precludes this approach in some markets.

Identification Using Physical Unclonable Functions

Another method of generating unique fingerprints is to utilize the inherent process variations in devices to create physically unclonable functions (PUFs). Random variations affect circuit properties, and by constructing the circuits sensitive to those properties, their behavioral differences can be utilized as IC IDs. PUFs using wire delays, gate delays, and ring oscillator frequencies have been proposed. The transistor threshold voltage (VT ) is directly dependent on random dopant fluctuations (RDFs), and is truly random, and thus ideally suited for PUFs. Su et al. proposed a VT mismatch-based identification method using crosscoupled NOR cells. Since RDF is the predominant cause of SRAM mismatch in mature processes, relying on VT strongly suggests using SRAMs for this function.

SRAM Power-Up State as an IC Identifier

SRAM is pervasive on modern ICs. The idea of using existing SRAM states during power-up as a fingerprint of the IC dates back to 2002 and has thoroughly been studied. Commercial SRAMs were powered up numerous times to calculate a statistically repeatable known-ID that was then used to authenticate any other fingerprints generated from further power-ups. Unfortunately, for embedded use, this scheme suffers from the drawbacks that include lack of support for ICs with built-in self-test (BIST) and that the resulting nonmatching codes may have considerably less than ideal code separation. BIST is required in many designs to set redundancy at power-up, which means that the SRAM state will not be random when available to software or hardware normal usage. In addition, the power-up SRAM cell state is influenced by process variations internal to the cell but importantly, by external noise. As the SRAM array is powered up, cells operate in the subthreshold region where they are most easily influenced by noise, potentially producing different power-up states up in different trials.

DISADVANTAGES:

  • Power consumption is high

PROPOSED SYSTEM:

SRAM power-up state was extensively studied as a PUF. All SRAM cells have built-in mismatch due to as-fabricated process variations. The SRAM cell is a crosscoupled inverter pair with a built-in voltage offset (VOFFSET) due to RDFs, i.e., threshold voltage (VT) and other transistor, as well as node capacitance mismatches. Under normal conditions, the SRAM cell’s internal nodes, D and Q, shown in Fig. 2(a), are in one of two stable states DQ = 01 or DQ = 10. States DQ = 11 and 00 are unstable and thus unreachable in the normal operation. When the circuit is powered down (VDD = 0 V), the nodes D and Q are in the unstable 00 state.

Fig. 1. (a) Part of the test SRAM showing the decoder and SRAM array with different power supply voltages used to generate the IDs. Note that the circuit becomes identical to the traditional 6-T structure when VDDARRAY = VDD. (b) Write circuit to implement the BL_Low method. In normal operation, the ID_enable signal is deasserted and the data and its inverse appear on BL and BLN. However, when the ID_enable signal is asserted, both BL and BLN are forced toward VSS.

Proposed Methods and Principle of Operation

In contrast to using power-up, in both the methods proposed here, we force the SRAM into a metastable state (DQ = 11 or DQ = 00), with VDD applied to the SRAM cells. Thus, the SRAM state can be checked at times other than power-up, for instance, after BIST or as requested by a software application.

Fig. 2. (a) BL_High method drives current primarily through the nMOS access and pull-down devices NA0–N0 and NA1–NA1, respectively. (b) SRAM cell internal node (D and Q) waveforms applying the proposed method with both BLs driven to 1 V—BL voltages below show that the BLs cannot reach 1 V due to the strong nMOS pull-down transistors inside the cell. The WL is driven to a higher voltage (1.5 V here) to destabilize the cell and to 1 V, the nominal VDD (1 V here) to read out the value.

The overall operation of a word of SRAM as a PUF is similar to a sense amplifier, whereby the small voltage difference due to VOFFSET is amplified when the cross-coupled inverters are freed after the SRAM cell is driven to a metastable state. To force the nodes D and Q into the metastable state close to 11, the cell must be destabilized. To accomplish this, the access nMOS transistors are strengthened with respect to the pull-down transistors. This is accomplished by altering the voltages at the array level. Thus, the access transistors are made stronger than the pull-down nMOS transistors by increasing their gate overdrive, i.e., setting the word-line (WL) voltage VWL above the array supply voltage VDDARRAY when the fingerprint is taken [see Fig. 1(a)].

Method BL_High (BLs = 1)

For normal applications, the SRAM is read or written by driving the SRAM row WL to VDD = VDDARRAY. To implement the BL_High method, the timing and control circuits are modified to allow the BLs to be precharged, while VWL = VDD > VDDARRAY destabilizes the cell.

Method BL_Low (BLs = 0)

In this proposed method, the BLs are driven toward 0 V by simultaneously writing a logic 0 to each BL. In this scheme, the dominant ratio is that between the pull-up pMOS and the access nMOS transistors, e.g., P0 and NA0, respectively, as shown in Fig. 3(a). In this proposed method, the SRAM cell internal nodes are forced to metastable voltages close, but slightly greater than the 00 power-up point. The SRAM cell is easily destabilized even without the higher voltage on the WL. Therefore, the greater than VDDARRAY VWL voltage is not required.

Fig. 3. (a) BL_Low method drives current primarily through the nMOS access and pull-up pMOS devices NA0 from P0 and NA1 from P1, respectively. (b) Waveforms applying the proposed method with both BLs = 0 V—when driven metastable, the BLs near 0 V, since the pMOS transistors must be weak to ensure normal write-ability.

Circuit Operation

Although in both methods, the SRAM cell is forced to a metastable state, the bit-line voltage amplitude plays a significant role in determining the mismatch in the internal nodes’ VD − VQ (offset) voltage. The SRAM circuits in Figs. 2(a) and 3(a) illustrate the primary current flow through the access transistor NA0 and NA1 that creates the different voltages at nodes D and Q under different BL conditions, projecting the mismatch onto the SRAM cell logical state when the WL is deasserted.

ADVANTAGES:

  • Power consumption is reduced

SOFTWARE IMPLEMENTATION:

  • Tanner tools
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