Power-Efficient Gm-C DSMs With High Immunity to Aliasing, Clock Jitter, and ISI

Power-Efficient Gm-C DSMs With High Immunity to Aliasing, Clock Jitter, and ISI


Recent progress in continuous-time (CT) Delta– Sigma modulators (DSMs) research has shown that applying a passive RC low-pass filter (LPF) in the feedback path can significantly improve the power efficiency of a CT DSM. On the other hand, to achieve high performance, a CT DSM faces the adverse effects of clock jitter, inter symbol interference (ISI), or degradation of anti aliasing ability. These challenges are extremely difficult to tackle simultaneously without consuming excessive power. This paper proposes a Gm-C DSM with a combined RC and switched-capacitor LPF frontend stage to achieve a high performance against aliasing, clock jitter, and ISI simultaneously while having an extremely low power consumption. Transistor level simulations on an audio band modulator and a 10-MHz bandwidth modulator are given, verifying the high immunity of the proposed circuit to clock jitter, ISI, and aliasing while attaining a power efficiency up to 7.4 fJ/conversion step.


DELTA–SIGMA modulators (DSMs) have been applied in a variety of electronic products from biomedical devices with a narrow frequency range of dozens of Hertz to wireless communication networks with a bandwidth up to tens of megahertz or higher. Oversampling and spectral shaping of quantization noise allow a modulator to use low-quality components, such as amplifiers with low gain and comparators with relaxed offset, to achieve high resolution. There are mainly two types of implementations: discrete-time (DT) DSMs and continuous time (CT) DSMs. CT DSMs are attractive due to their constant input impedance, anti aliasing feature and relaxed bandwidth, and the slew-rate requirement of amplifiers compared with their counterparts implemented by switched-capacitor (SC) circuits. A constant input impedance gets rid of the signal dependent charge injection associated with an SC input, makes the input current smoother than the rapidly changing current pulses in an SC input, thereby reduces the power of the input buffer, contributing to the reduction of the power of the whole system. The anti aliasing ability leads to the elimination of the frontend filters, which also saves power for the whole system. A pure Gm-C implementation presented in achieves very high resolution but has a very limited input range. In, a resistor input and a multi bit feedback DAC are proposed to realize a subtractor to generate a rough virtual ground before the Gm-C integrator, but a source-degenerated trans conductor is still needed to enhance the linear input range, which greatly degrades the power efficiency of the Gm-C loop filter. Recent publications point out that applying a passive RC low pass filter (LPF) in a CT DSM can significantly improve its power efficiency by attenuating the swing of the error signal to its first and most crucial active integrator.

On the other hand, CT DSMs suffer from clock jitter and inter symbol interference (ISI). These problems become more pronounced in high-resolution and wide bandwidth designs. Traditional methods to reduce the sensitivity to clock jitter include the use of SC DACs and the finite-impulse response (FIR) DACs. An SC DAC possesses high immunity to clock jitter because the aperture uncertainty only affects the small tail of the SC current pulses. However, the steep current pulses increase the output settling requirements of the first amplifier to extremes, thereby significantly increasing the power consumption. Moreover, the conventional SC DAC degrades the anti aliasing ability, a fundamental advantage of CT DSMs, because of the sampling operation at the virtual ground of the first amplifier. The FIR DAC approach, despite its success in jitter reduction, requires a second FIR filter to maintain the loop stability, increases the total load resistance (when the DAC is resistive loaded) by a factor of 2N2 (N is the number of FIR taps), draws dynamic power consumption in its driving circuits, and is still sensitive to ISI when the non-return-to zero (NRZ) signaling is applied.

The ISI in a single-bit DAC results from the asymmetrical rise and fall times of the DAC’s output waveform. The effect of ISI in an NRZ DAC can be reduced by calibration approaches and ISI error shaping methods. However, they are complex circuits and consume extra power. Another approach to the ISI problem is to use a return-to-open (RTO) DAC or a return-to-zero (RZ) DAC. However, to keep the same full-scale value, an RZ/RTO DAC needs to increase the height of feedback current pulses, which increases the power consumption of the amplifier to retain the same linearity. In addition, the widely used rectangular-shape RZ DAC is more sensitive to clock jitter than an NRZ DAC.

The problems of clock jitter, ISI, and aliasing are extremely difficult to tackle simultaneously without consuming excessive power. In this paper, a new single-bit CT DSM is proposed with high-power efficiency and high immunity to clock jitter, ISI, and aliasing at the same time. The CT DSM has a combined passive RC and SC LPF frontend stage followed by a trans conductance-C (Gm-C) loop filter. To demonstrate the effectiveness of the proposed structure, two modulators are designed: one with an audio bandwidth (25 kHz) and the other a wider bandwidth (10 MHz) for mobile wireless receiver applications. Transistor-level simulations show that the audio band design achieves 95- dB signal-to-noise-and-distortion ratio (SNDR) with 49 μW in a 0.18-μm CMOS, corresponding to Walden’s figureof-merits (FoMW ) of 21.3fJ/conversion step; the wideband (10 MHz) example achieves 81-dB SNDR while consuming 1.36 mW in a 65-nm CMOS, corresponding to an FoMW of 7.4fJ/conversion step.


  • High gain and High resolution
  • High power efficiency
  • More Clock jitter



In spite of its high linearity, the CT DSM of Fig. 1(d) suffers from clock jitter and ISI in circuit implementation. In this section, we present a frontend circuit to address these problems. The proposed Gm-C CT DSM circuit architecture is shown in Fig. 2(a). The PI bock (k1s + 1/s) in Fig. 1(d) is realized by gm2, RE , and C3, where the excessive loop delay is compensated by RE and requires no additional active circuit. The dash-boxed part is a combined SC (for the feedback signal) and RC (for the input signal) LPF, short-handed as RSC-LPF. The RSC-LPF makes the Gm-C modulator immune to clock jitter, ISI, and aliasing while achieving a high power efficiency.

Figure 1:  Third-order CT DSMs with (a) simple single-bit approach; (b) 3-bit quantizer; (c) single-bit quantizer and a seven-tap FIR NRZ DAC; and (d) single-bit quantizer and an LPF. Nonlinearities in the first active integrators are modeled

To appreciate the development of the RSC-LPF, let us start with the approach of using an RC LPF for both the input and feedback signals, as shown in Fig. 2(b). The transfer function of this circuit is given by

ε(s)/ VIN(s) = 1/ 2 + s RinCP            (8)

where the pole location of the LPF is determined by the RinCP constant. By balancing the tradeoff between the in-band quantization noise and thermal noise, placing the pole at the signal band edge is a proper choice [8]. The resistive path for the feedback can implement an NRZ or RZ DAC, however, being sensitive to clock jitter. To suppress the effect of clock jitter, R f is replaced with a capacitor C1 switched at the sampling frequency fs, as shown in Fig. 2(c). Normally, R f equals Rin. The choice of their values is discussed in Section VII. When f fs, i.e., in the signal band, the switched capacitor C1 emulates a resistor of value Req = Ts/C1, where Ts = 1/ fs. The transfer function from VIN to ε is still given by (8) in the signal band. There are tiny differences at multiples of the sampling frequency, which will be explained in Section VI. The transfer function from VF to ε is

ε(z)/VF (z) = (C1 /C1+CP) /(z − (CP−C1/C1+CP)) = α / (z − (1 − 2α), α = C1 C1 + CP .    (9)

Equation (9) is equivalent to (8) when f fs under the condition of Ts = RinC1. A very small signal ε is left for the subsequent open-loop Gm-C integrator to handle, freeing it from linearity and slew-rate constrains to save power.

A fundamental difference exists between the proposed RSC-LPF approach and the SCR DAC approach [11], which looks similar. The SCR DAC must be assisted by a closed loop OTA and thus imposes settling requirements on the OTA. By contrast, in the proposed approach, the charging and discharging of C1 in the SC DAC does not involve the OTA, and thus does not impose any settling requirements on it. This leads to a significant improvement in power efficiency.


Figure 2 : (a) Proposed Gm-C CT DSM with an RSC LPF front end, where V is the digital output data, VF is the feedback signal, DAC2 is a current steering DAC. (b) RC LPF. (c) RSC LPF alone

In Fig. 2(a), the speed of charge redistribution between C1 and CP is determined by the ON-resistances of the switches. The transistors realizing the switches can be sized to minimize their ON-resistances, as the charge injection is not an issue for the following reason. Since VF has only two possible values and ε is nearly a virtual ground, for either the level of VF , the amount of the charge injected from the switches is fixed. The switch charge injection only results in an offset or gain error but not nonlinearity.

The values of Rin, C1, and CP can be determined with the following procedures.

1) The ratio between the full ranges of the input and the feedback is fixed. Normally Rin = Req is chosen for equal input and feedback ranges.

2) The value of Rin is determined by the thermal noise requirement based on (28) in Section VII.

3) By RinCP = (1/2π · BW), where BW is the signal bandwidth and CP is found.

4) By Ts = ReqC1 = RinC1, C1 can be derived.

A mismatch between Rin and R f (=Ts/C1) of the feedback SC causes a change in the pole frequency of the LPF for both VIN and VF (by the same proportion). The result is only a scaling of VIN with respect to VF . Simulations have validated that the modulator can tolerate a ±40% mismatch between Rin and Req without significant performance degradation. When the modulator loop works normally, the node ε in Fig. 3(a) with a small swing can be regarded as a virtual ground. Thus, the load to the preceding stage of the modulator can be regarded as a purely resistive of value Rin. On the other hand, before the modulator loop is locked, which is a negligibly short period, the feedback signal VF does not cancel the input signal and the node ε is not a virtual ground. The input impedance is (1 + s RinCP)/sCP, which has the magnitude always larger than Rin and is easier to drive


  • Low gain and Low resolution
  • Low power efficiency
  • Low Clock jitter


[1] G. Singh, R. Wu, Y. Chae, and K. A. A. Makinwa, “A 20 bit continuoustime  modulator with a Gm-C integrator, 120 dB CMRR and 15 ppm INL,” in Proc. ESSCIRC, Sep. 2012, pp. 385–388.

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