Multiloop Control for Fast Transient DC–DC Converter

Multiloop Control for Fast Transient DC–DC Converter


A novel ac coupled feedback (ACCF) is proposed to alternatively realize fast transient response while inherently controlling the start-up in-rush current of a dc–dc switching converter. The proposed ACCF is modified from a conventional capacitor multiplier and connected between the outputs of the converter and the transconductance. With this supplemental feedback, the transient response has been significantly improved due to the gain-boosting effect around the compensator’s midband. Moreover, the ACCF circuit assists to manage the ramping speed of the output voltage during power-up, thereby eliminating the bulky soft-start circuit. The new controller is very simple to implement and occupies a tiny footprint on-chip. A buck converter with the proposed scheme has been fabricated using the 0.18-µm standard CMOS process with an active silicon area of 0.573 mm2. Measurement results show that the output voltage rises linearly for a soft-start period of 1.05 ms according to the designed slope. Excellent load transient responses are achieved under different load current steps; the output voltage overshoot/undershoot of 60 mV settles down within 10 µs for a load variation from 50 µA to 1 A in 1 µs. Moreover, the proposed converter maintains both excellent load and line regulations of 0.018 mV/mA and 0.0056 mV/mV, respectively.





  • Design of fast transient DC-DC convertor implemented in 45nm CMOS technology, and vary input voltage 2.6V ~ 4.2V.

Proposed Title:

  • An Efficient Approach of Fast Transient DC-DC Convertor using Multiloop Control

Proposed Abstract:

Step-down method ofDC -to-DC power converter it is called Buck Converter. The operation of electromechanical device of DC-DC converter is converts direct current (DC) from certain level of input voltage to another voltage level. This paper proposes the novel design implementation of fast transient response current-mode buck converter with ac coupled feedback (ACCF). Where, ACCF is the modified design of a conventional Capacitor multiplier. The previous method of DC to DC Converters requires more power to achieve the fast transient to voltage conversion and it has high electromagnetic interface (EMI) noise. To overcome this problem this work presents a novel design of DC-DC converter with ACCF. ACCF circuit used to eliminate the bulky soft-start circuit when the ramping speeds of the output voltage during power-up. A Present Proposed system uses current mode- controller to improve response in speed and also increasing load transient voltages. The proposed scheme has been implemented in input voltage 2.6V ~ 4.2V and 45nm CMOS technology and compared in terms of Voltage, power, area and delay of the DC-DC converter will be calculated.


THE demand for fast load transient performance has grown significantly, affecting the power supplies of modern high-speed processors—especially processors targeting to achieve a fast transition from the low-power idle mode to the high-speed active mode. There is a massive load current change when the system switches from an idle mode to an active mode. Ideally, the regulator should maintain a voltage level that is almost constant, which means that there should be a negligible output voltage overshoot/undershoot and rapid response time. To accomplish these stringent requirements, various research works on fast transient dc–dc converters have been proposed.

Among these methods, the increase of system bandwidth has been the most general solution for the majority of the analog circuits designed according to the linear control theory. In the design of a switching mode dc–dc converter, the wide system bandwidth can be achieved by adopting the current-mode control method. On top of that, an adaptive pole–zero position circuit has been proposed to instantly move the pole and zero pair of the compensation network to higher frequencies, in order to temporarily extend the bandwidth of the system during the transient event. The pole and zero are moved back immediately after the transient event to stabilize the system. However, a careful design targeting system stability during the whole process needs to be taken into consideration once the bandwidth is tentatively changed. Another commonly used method to improve the transient response is to increase of the slew rate of the error amplifier.

Different current-boosting modules are used to increase the source/sink current at the output of the error amplifier during the transient period. The required boosting current must be large enough to realize an obvious improvement on the transient response, and at the same time, it needs to avoid the over-response oscillation caused by the excessive boosting current. Moreover, current-boosting modules introduce more power consumption, which degrades the overall efficiency.

Besides that, the use of nonlinear control is an alternative to realize fast transient response. For example, hysteresis control can offer immediate feedback during load variations. However, this method has a drawback—the high electromagnetic interference (EMI) noise due to its variable switching frequencies. Circuits can be added to lock the switching frequency and thus abate the EMI noise, but such additions bring more complexities into the circuit design.

Figure 1: Conventional current-mode buck converter with the proposed ACCF loop

Figure 2: Type-II compensation designs. (a) OpAmp–RC topology. (b) Gm–C topology


The conventional current-mode buck dc–dc converter is highlighted with the blue dashed line. Differing from the conventional type-III compensation network which contains three poles and two zeros to boost the phase to ensure stability, the proposed method generates the same number of poles and zeros to boost the mid-band gain to significantly enhance the response strength of the compensator, thus increasing the transient response. At the same time, the proposed scheme also helps to manage the output voltage ramping speed during the converter power-up.

Theoretically, the transient performance depends mainly on two factors—the response speed and the response strength. The former can be interpreted as the delay time from the load transient event to the change on the control signal, and the latter refers to the amount of the amplitude changes on the control signal. Taking the widely used type-II compensation design as an example here, the structure of the type-II compensation designs can be realized by either the operational amplifier–resistor–capacitor (OpAmp–RC) topology [as shown in Fig. 2(a)] or the transconductance–capacitor (Gm–C) topology [as shown in Fig. 2(b)]. During the load step, the variation in the output voltage results in a change in the feedback signal . The control signal Vc can only respond gradually, due to the compensator’s integrating effect. Its response speed depends on the bandwidth of the compensator. Assuming an error voltage Verr turns up on the feedback, the amount of change of the control signal (|Vc|) from its steady-state level can be expressed in the following equations for the


OpAmp–RC and Gm–C topologies, respectively [1]:

where Verr stands for the error voltage that turns up on the feedback, gm0 is the transconductance of the gm0 cell, and Rfb and Rc are the resistors connected to the inverting input terminal of the OpAmp and the compensation resistor, respectively.



  • Difficult to achieve fast load transient performance.
  • Current boosting modules in existing system require more power, which degrades the overall efficiency.
  • High electromagnetic interface (EMI) noise.




This paper utilizes a current-mode controller to improve the response speed aspect by increasing the system bandwidth in order to enhance the load transient response. On top of that, a novel ACCF is paralleled around the compensator to boost the response strength at the mid-band (as shown in Fig. 3), which is lacking in the conventional designs. The output impedances of both gm0 cell and ACCF are assumed to be infinity (which will be discussed in Section III). The transfer function of the conventional type-II compensation network can be expressed in (3) which includes two poles and one zero (located at p1, p2, and z1, respectively). With the additional ACCF, three poles and two zeros will be generated (located at p 1, p 2, p 3,z 1, and z 2, respectively), and the newly generated poles and zeros will boost the compensation mid-band gain as derived in (4). The respective Bode plot can be found in Fig. 4 accordingly

Without ACCF:

Figure 3: Proposed compensation network


where i1 and i2 are the output current from the gm0 cell and ACCF, respectively, α and α are constant coefficients, Ra and Rb are the voltage divider series resistors connected at the output of the dc–dc converter, and Cc1, Cc2, and Rc are the compensation capacitors and resistor, as shown in Fig. 3. Furthermore, the ACCF circuit also defines the output voltage rising slope during the converter power-up. The working principle of the soft-start function is illustrated in Fig. 5. During start-up, Vout is much lower than Vref, so that the gm0 cell will be saturated with an extremely high output voltage Vc, which will program an unfavorable runaway inductor current. With the help of the ACCF circuit, in this case, the fast-rising voltage appearing at Vout caused by the inrush start-up current is coupled through the ACCF and induces the ac current from Vc into the ACCF itself. As a result, Vc is pulled down to define the slow increase in the inductor current and output voltage. This particular inherent function of the proposed ACCF eliminates the need for a dedicated soft-start circuit in the conventional designs.

Figure 4: Illustration of the Bode magnitude plot of the buck converter with ACCF versus without ACCF.


Figure 5: Start-up response of the proposed controller.





  1. Active Compensation Capacitor

Active capacitor has been proposed and used in the amplifier to amplify capacitance in [21]. In this paper, the large passive compensation on-chip capacitor Cc1 is replaced by the equivalent active capacitor in the proposed buck converter to reduce the footprint, as shown in Fig. 6. The schematic of the active capacitor will be also modified and used in realizing the ACCF, which will be discussed later. Equations (5)–(7) explain the derivation of the equivalent active capacitor from the passive capacitor mathematically. The equivalent circuit of (7) is modeled in Fig. 6(b) as an active capacitor. The current mirror is used as the current control current source to amplify the ac current in this work. Fig. 7 shows the circuit implementation of the active capacitor by using the current mirror. A (N + 1) times smaller passive capacitor is utilized in parallel with the current mirror, which has an amplification factor of N (N = 19 in this paper), to realize the same capacitance as Cc1(Cc1 = 80 pF in this paper). Fig. 8 shows an approximately seven-time-reduction in the silicon area with the use of the equivalent active capacitor. The higher the value of N, the smaller is the footprint of the active capacitor.

Figure 6: Schematics of the equivalent capacitors. (a) Passive capacitor.(b) Active capacitor.

Figure 7: Circuit implementation of the active capacitor.


Nevertheless, the higher N with higher quiescent current will increase the static power consumptions. As a result, N needs to be designed at an optimized value

Passive capacitor



  1. Multiloop Control for Transient Enhancement and Soft-Start

The main structure of the ACCF circuit is modified from the active capacitor circuit , where an ordinary on-chip capacitor C f 1 is ac coupled from Vout, amplified by the current mirror (transistor M2-to-M1 with the ratio M:1, M > 1), and connected back to the main control loop at the gm0 cell output node, as shown in Fig. 9. The circuit implementation of the gm0 cell is shown in Fig. 10. Resistor Rgm is inserted in between the source terminals of MP1 and MP2 to sense the voltage differences (V) between the input terminals (V+ and V−) of the two super-source-followers; hence, gm0 of the cell will be inversely proportional to the value of Rgm . The output current is generated by the two pairs of current mirrors formed by MP3, MP4, MN3, and MN4 at the output stage, and it will charge the compensation network at the output of the gm0 cell. The mid-band gain (Amid-band) of the gm0 cell is, therefore, proportional to Rc while inversely proportional to Rgm , as expressed in (8). Eventually, the process, voltage and temperature variations of the two resistors are effectively canceled. Nevertheless, Rc should be placed close to Rgm in the layout for a better matching purpose

where Rc is the resistor in the compensation network at the output of the gm0 cell, and Rgm is the resistor in between the sources of MP1 and MP2.

Figure 8: Proposed current-mode buck converter.


Figure 9: Schematic of the gm0 cell.



The circuit implementation of the proposed ACCF realizes fast transient response as well as soft-start, which are analyzed in three aspects in the following.

1) Soft-Start Analysis: With the help of the ACCF, the fast rising voltage appearing at Vout caused by the start-up in-rush current will be coupled through C f 1. Then, an ac current will be inducted into the transistor M1. The M2-to-M1 current mirror is able to amplify the induced current and pull it from Vc; therefore, Vc is adjusted to a lower level. Consequently, Vc, inductor current, and Vout are well managed by the current control loop. The controllable soft-start slope is expressed in the following equation:

where Igm0_max is the maximum output current of the gm0 cell, M is the current ratio of transistor M2-to-M1, and C f 1 is the capacitor in the proposed ACCF.

2) Steady-State Analysis: The ACCF path is virtually disconnected from Vout during the steady state. The low pass filter R f 2C f 2 is added to prevent the Vout ripples from passing through the ACCF path and disturbing Vc. It is designed to cut off around the converter’s switching frequency. Although there is no current flowing between the gm0 cell and the ACCF circuit, the output impedance of the gm0 cell is reduced due to the ACCF output stage. The advanced current mirror with high output impedance should be considered on condition that a large dc loop gain is preferred.

3) Transient Analysis: As discussed previously, the load transient performance is improved on account of the gain boosting effect around the compensator’s mid-band. This can be understood analytically by deriving the transfer function from the small-signal equivalent circuit, as shown in Fig. 11(a). The transconductance of the transistors M1 and M2 are labeled as gm1 and gm2 (gm2 = Mgm1), and RO represents the combined output impedances of the gm0 cell and the ACCF. The original single-loop compensation capacitor Cc1 still determines the dominant pole in this multiloop network.

  1. Continuous-Sensing-Technique for Fast-Response Current Sensor

The current sensor has been used to sense the inductor current in the current-mode dc–dc converter. The conventional design is shown, where a sense FET (SenFET) is implemented to sense the current passing through the high side power FET MP at the ratio of k to 1 (k

1). MP and Ms1 are switched ON simultaneously when the gate control signal Q is low. Meanwhile, the current sensor works in the “active sensing mode” and the SenFET keeps tracking the current passing through MP using an almost equalized drain-to-source voltage level. In the other words, Va is adaptively adjusted to Vb through the feedback of OpAmp. The outputs of the current sensor are isenc and Vsenc, which represent the sensed current and voltage with the required ratios, respectively. Alternatively, Vb will be at the same voltage level as Vin in the case where Ms2 is switched ON by the high Q signal (Q¯ connected at the gate of Ms2 represents the complement signal of Q). In this situation, Vb equals to Vin as well as Va, the output sensed current isenc is negligible. The OpAmp is in its “sleeping mode.” The current sensor will only change back to the “active sensing mode” once Q switches from high to low in the next switching phase, which means that the OpAmp is required to “wake up” instantly thus to accurately sense the current passing through MP by tracking the changes at node Vb. However, the reaction time that the OpAmp needs to adjust itself from one set of dc operating points to the other must be considered. It causes delays (tdelay) at the beginning of every sensing stage as illustrated in Fig. 13—the blue dashed line represents the sensed MP current by the conventional current sensor and the red solid line represents the ideally sensed inductor current. Obviously, the problem will become more severe when the on-time of MP is short.

To solve the stated problem, a continuous-sensing-technique is proposed to sense the current passing through MP without any delay (tdelay). As shown in Fig. 14, the proposed current sensor consists of two sensing stages, namely, the high side current sensing stage (which senses the power PMOS MP drain current when Q is low) and the low side current sensing stage (which senses the power NMOS MN drain current when Q is high). The low side sensed MN current (isenN2) will be connected to the high side current sensing stage through MH and MPS2. With that, the high side current sensing stage senses the MP drain current when Q is low. Mps2 will be turned ON and the current introduced by the low side current sensor (isenN2) will be connected to the high side current sensing stage once Mps1 is switched OFF when Q is high. With this additional current source, the high side current sensing stage will continuously be active and sense the current isenN2 by tracking Vpa to Vpb. Mps2 will be switched OFF while Mps1 and Mp are switched ON when Q changes to low, and the power MOSFET sensing mode will then be active again. There is no delay in between the two switching phases because the two input nodes of the OpAmp (Vpa and Vpb) are continuously well-controlled, so do the dc operating points. Since no “wake up” time is needed, there is no delay for the high side current sensing stage. The delay at the low side current sensing stage will not affect the sensing accuracy in the peak current-mode control. The simulation results can be found in Fig. 15. The output voltage/current (Vsenp/Isenp) of the current sensor is proved to have negligible delays.

Figure 10: Proposed continuous-sensing current sensor.



  • Fast load transient performance has been achieved.
  • Low power consumption.
  • Low electromagnetic interface (EMI) noise.

Literature Survey:

  • Zhou, Z. Sun, Q. Low, and L. Siek, “Fast transient response DC–DC converter with start-up in-rush current control,” Electron. Lett., vol. 52, no. 22, pp. 1883–1885, Oct. 2016.–A new alternative to achieve fast transient response while inherently managing the in-rush current during DC/DC switching converter start-up is proposed. An AC coupled feedback (ACCF) is introduced using a capacitor multiplier from the output of the converter to the output of the error amplifier. With this additional feedback, the transient response, which used to be limited by the compensator mid-band gain has been significantly improved. Meanwhile, the ACCF circuit can help to control the converter output ramping speed during power-up, thus eliminating the bulky soft-start circuit. The simplified circuit design means the new controller can be realised by a tiny on-chip circuit, thereby minimising the footprint and the cost. A buck converter with the proposed technique is designed using 0.18 μm CMOS process and simulated across different process corners. Simulation shows that the output voltage increases linearly with the designed slope despite the variations of the input voltage, inductor or output capacitor values. An excellent load transient response of 0.021 mV/mA is achieved for a load current variation from 50 μA to 1 A in 1 μs.
  • -Y. Hsieh and K.-H. Chen, “Adaptive pole-zero position (APZP) technique of regulated power supply for improving SNR,” IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2949–2963, Nov. 2008.– This paper proposes an adaptive pole-zero position (APZP) technique to achieve excellent transient response of dc–dc converters. The APZP technique triggers the two-step nonlinear control mechanism to speed up the transient response at the beginning of load variations. Before the output voltage is regulated back to its voltage level, the APZP technique merely functions as a linear control method to regulate output voltage in order to ensure the stability of the system. Fast transient response time, low output ripples, and stable transient operation are achieved at the same time by the proposed APZP technique. Experimental results in the UMC 0.18- mum process show that the transient undershoot/overshoot voltage and the recovery time do not exceed 48 mV and 10 mus , respectively. Compared with conventional design without any fast transient technique, the performances of overshoot voltage and recovery time are enhanced by 37.2% and 77.8%. With the APZP technique, the performance of dc–dc converters is improved significantly.
  • -H. Lee, S.-C. Huang, S.-W. Wang, and K.-H. Chen, “Fast transient (FT) technique with adaptive phase margin (APM) for current mode DC-DC buck converters,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 10, pp. 1781–1793, Oct. 2012. This paper proposes a fast transient (FT) control with the adaptive phase margin (APM) to achieve good transient response in current-mode DC-DC buck converters at different load conditions. The overshoot/undershoot voltage and the transient recovery time are effectively reduced. The APM control can always maintain the system phase margin at an adequate value under different load conditions. That is, the compensation pole-zero pair is adapted to load current to extend the system bandwidth and get an adequate phase margin. Experimental results show the overshoot/undershoot voltage is smaller than 60 mV (3%) and transient period is smaller than 12 μs as load current suddenly changes from 100 to 500 mA, or vice versa. Compared with conventional designs without any fast transient technique, the undershoot voltage and recovery time are enhanced by 45% and 85%, respectively.
  • F. Lee and P. K. T. Mok, “A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 3–14, Jan. 2004. A monolithic current-mode CMOS DC-DC converter with integrated power switches and a novel on-chip current sensor for feedback control is presented in this paper. With the proposed accurate on-chip current sensor, the sensed inductor current, combined with the internal ramp signal, can be used for current-mode DC-DC converter feedback control. In addition, no external components and no extra I/O pins are needed for the current-mode controller. The DC-DC converter has been fabricated with a standard 0.6-/spl mu/m CMOS process. The measured absolute error between the sensed signal and the inductor current is less than 4%. Experimental results show that this converter with on-chip current sensor can operate from 300 kHz to 1 MHz with supply voltage from 3 to 5.2 V, which is suitable for single-cell lithium-ion battery supply applications. The output ripple voltage is about 20 mV with a 10-/spl mu/F off-chip capacitor and 4.7-/spl mu/H off-chip inductor. The power efficiency is over 80% for load current from 50 to 450 mA.
  • Y. Leung, P. K. T. Mok, K. N. Leung, and M. Chan, “An integrated CMOS current-sensing circuit for low-voltage current-mode buck regulator,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 7, pp. 394–397, Jul. 2005. An integrated current-sensing circuit for low-voltage buck regulator is presented. The minimum achievable supply voltage of the proposed current-sensing circuit is 1.2 V implemented in a CMOS technology with V/sub TH/=0.85 V, and the current-sensing accuracy is higher than 94%. With the developed current-sensing circuit, a buck regulator, which is able to operate at a 1.2-V supply, is implemented. A maximum output current of 120 mA and power-conversion efficiency higher than 89% are achieved.
  • -I. Wu, B.-T. Hwang, and C. C.-P. Chen, “Synchronous double pumping technique for integrated current-mode PWM DC–DC converters demand on fast-transient response,” IEEE Trans. Power Electron., vol. 32, no. 1, pp. 849–865, Jan. 2017. While the fast transient techniques have been extensively investigated, the research aiming at current-mode pulse width modulation (PWM) converters is relatively unexplored. This paper presents a synchronous double-pumping (SDP) technique for current-mode PWM dc-dc converters to achieve fast-transient response between different load conditions. The advantages and limitations of the existing conventional techniques are discussed and analyzed. With the proposed SDP technique, a nearly optimized recovery time speedup and voltage drop minimization for every different conventional current-mode converters can be obtained. The prototype chip was fabricated using a TSMC 0.35-μm CMOS process occupies the area of 2.242 mm 2including all bonding pads and ESD protection circuits. The output voltage ripple is measured about 15 mV in peak-to-peak value. The recovery time is 2.4 and 2.6 μs, respectively, in response to the 400-mA step-up and step-down load changes. Those are improved by a factor of 8.33 and 8.23, respectively.
  • -H. Lee, K.-Y. Chu, C.-J. Shih, and K.-H. Chen, “Proportional compensated buck converter with a differential-in differential-out (DIDO) error amplifier and load regulation enhancement (LRE) mechanism,” IEEE Trans. Power Electron., vol. 27, no. 5, pp. 2426–2436, May 2012. A differential-in differential-out error amplifier and a load regulation enhancement mechanism are proposed in the buck converter that aims to improve load regulation and noise immunity. By using the proportional compensator in the proposed converter, there is no need of external compensation components in this design. As a result, a compact-size and high-performance dc-dc buck converter can be guaranteed. Experimental results show that load regulation can be improved from 0.5 to 0.025 mV/mA. The test chip was fabricated by 0.25 μm CMOS process and occupied 1.65 mm active silicon area.
  • -J. Liu, T.-H. Chen, and S.-R. Hsu, “Area-efficient error amplifier with current-boosting module for fast-transient buck converters,” IET Power Electron., vol. 9, no. 10, pp. 2147–2153, Aug. 2016. The current boosting module (CBM) is proposed to be implemented in an error amplifier (EA) for improving the load transient of a dc-dc converter. To enhance the slew rate of the EA during transient, the CBM is adopted to raise/reduce the gate voltages of the output-stage transistors of the EA for enhancing its current driving capability with simple circuitry. Moreover, to save power consumption in steady state, the accelerative mechanism of the EA is turned off. A buck converter with CBM is implemented with 0.35 μm 2P4M complementary metal-oxide-semiconductor process. The experimental results demonstrate that the recovery time and transient ripple of the buck converter are improved by over ten times and two times, respectively, compared with those of the buck converter without CBM, for a 450 mA load current change. The maximum power conversion efficiency is 92.8% when the input and output voltages are 4 and 2.5 V, respectively. Hence, the buck converter with CBM can concurrently fulfil the functionalities of fixed switching frequency and fast load transient.


[1] M. Zhou, Z. Sun, Q. Low, and L. Siek, “Fast transient response DC–DC converter with start-up in-rush current control,” Electron. Lett., vol. 52, no. 22, pp. 1883–1885, Oct. 2016.

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