Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping

Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping

ABSTRACT:

This paper presents two new line-coding schemes, integrated pulse width modulation (iPWM) and consecutive digit chopping (CDC) for equalizing lossy wire line channels with the aim of achieving energy efficient wire line communication. The proposed technology friendly encoding schemes are able to overcome the fundamental limitations imposed by Manchester or pulse-width modulation encoding on high-speed wire line transceivers. A highly digital encoder architecture is leveraged to implement the proposed iPWM and CDC encoding. Energy-efficient operation of the proposed encoding is demonstrated on a high-speed wire line transceiver that can operate from 10 to 18 Gb/s. Fabricated in a 65-nm CMOS process, the transceiver operates with supply voltages of 0.9 V, 1 V, and 1.1 V. With the help of the proposed iPWM encoding, the transceiver can equalize over 27-dB of channel loss while operating at 16 Gb/s with an efficiency of 4.37 pJ/bit. The design occupies an active die area of 0.21 mm2.

EXISTING SYSTEM:

GROWTH of online video content for high resolution (4k, 8k) video, and data generated by IoT devices has resulted in an exponential increase in the data rates at each and every point in the communication chain from data centers to smart phones. Wire line communication system addresses the bandwidth demand in two ways: (1) by increasing the number of channels and (2) by increasing the data rate per channel. Increasing the channels typically requires investment in new infrastructure, and is therefore discouraged. Consequently, increasing the data rates per channel has been the trend in wireline links over the last 16 years, as shown in Fig. 1(a). While the energy efficiency of these links has continued to improve, the efficiency improvement has slowed down in the last six years, as shown in Fig. 1(b).

A major reason for the slowdown in energy efficiency improvement is the fact that, while data rates continue to increase, communication channels have remained more or less same since channel upgrades are very expensive. The same channel at higher data rates results in more inter-symbol interference (ISI), which requires greater equalization to compensate the channel loss. Equalization of the channel loss consumes significant power and degrades the energy efficiency of the wire line communication link.

Conventional equalization techniques on the receiver end such as decision feedback equalizers have tight feedback timing constraints, which result in higher power consumption as the data rate increases. Feed forward equalization (FFE) on the transmitter with voltage mode driver avoids the feedback path and results in efficient equalization. Based on the FFE tap resolution requirement, the output driver and pre-driver are divided into multiple segments. Although such a segmented FFE implementation helps to maintain a constant output termination impedance (50) across all tap settings, it comes at the cost of (a) increased signaling power, (b) increased switching power since multiple segments are required to achieve desired linearity, and (c) tight coupling between 50 termination tuning and FFE tap coefficients tuning. These three constraints reduce the FFE efficiency as the number of FFE taps are increased to equalize heavy channel loss.

Figure 1 : (a) Data rate vs. year of wire line link publication. (b) Energy efficiency vs. year of publication

Conventional line-coding techniques such as Manchester encoding (also known as pulse width modulation or PWM), can equalize the wire line channel without increasing signaling power, without segmenting the output driver, and without coupling the 50 termination tuning with the coefficient tuning. However, PWM encoding requires the insertion of a precise narrow pulse in every data bit. These narrow pulses must be accurately reproduced at the transmitter output, which necessitates very wide bandwidth in the high-speed data path, resulting in poor energy efficiency and difficulty in scaling PWM encoding to higher data rates. For example, creating a 10% duty cycle on a 64Gb/s PWM data stream would require a pulse width of 1.5ps with less than 1ps of rise/fall time at the transmitter output. Researchers have shown that phase pre-emphasis encoding scheme can help to reduce data dependent jitter. However, it is ineffective at equalizing high-loss channels.

In view of these limitations, we propose two highly-digital phase-domain line-coding/modulation technique for equalization: (a) integrated pulse width modulation (iPWM) and (b) consecutive digit chopping (CDC). The proposed iPWM technique can compensate more than 27dB of channel loss at 16Gb/s while consuming 69.9mW of power. Compared to the state-of-the-art PWM designs, the proposed iPWM scheme achieves 36× better energy efficiency for the same data rate, and 3.2× higher data rate for the same energy efficiency. The proposed CDC encoding technique in tandem with iPWM, can equalize a channel loss of upto 30dB at 14Gb/s.

In the past, researches have also proposed digital phase modulation techniques such as pulse width modulation (PWM) to encode the information in pulse widths instead of voltage levels (example: PAM-4/8/16). This work differentiates itself from the prior PWM based modulation research by the fact that the proposed work presents line-coding technique to equalize a wireline channel and it does not modulate the pulse width to encode information. In the proposed work, the information is contained in the two voltage levels only.

DISADVANTAGES:

  • Number of Channels is very low
  • Low Data rate
  • More area and power consumptions

PROPOSED SYSTEM:

Wireline communication channels have low-pass characteristics. That is insertion loss of the channel increases with frequency. Let’s say the data through the channel has 0 consecutive identical digits (CIDs), that is, the data is an alternating data (101010…), whose power spectrum is limited to just one frequency. With such data, the loss offered by the channel is constant and there is no ISI (no eye closure), as shown in Fig. 2(a). In reality, the transmitted data has consecutive identical digits (CIDs) such as 10110 (2 CIDs), 01110 (3 CIDs), 11110 (4 CIDs), etc, which causes the power spectral density of the data to have a wide bandwidth. Because of frequency dependent insertion loss of the channel, the loss offered to 4 CIDs is less as compared 3 CIDs or 2 CIDs because the majority of the power spectrum of data with 4 CIDs is located at a lower frequency as compared to the power spectrum of data with 3 CIDs and 2 CIDs.

Figure 2 : (a) Effect of consecutive identical digits on inter-symbol interference (ISI). (b) Time domain pulse response of NRZ data and proposed iPWM encoded data in the presence of CIDs

As a result, the data with 4 CIDs has a higher amplitude at the channel output than the data with 3 CIDs and 2 CIDs. Consequently, the transition time to a bit of opposite polarity immediately following the CIDs is higher for 4 CIDs as compared to 3 CIDs and 2 CIDs. The long transition time reduces the horizontal and vertical eye opening of the data bit immediately following the CIDs. Hence, due to the difference in the insertion loss offered to CIDs, the data bit immediately following the CIDs, suffers from inter-symbol-interference (see Fig. 2(a)).

The proposed iPWM operates on the fact that the ISI on the data bits following the CIDs can be reduced by reducing the pulse width of CIDs at the transmitter. The concept of reducing the pulse width is graphically explained in Fig. 2(b). In the proposed iPWM, instead of transmitting 2 CIDs for the complete duration of 2 UI (unit interval), 2 CIDs are transmitted for less than 2 UI. As a result, the transition to the bit of opposite polarity happen early, in other words, the post-cursors generated by 2 CIDs is reduced, which helps to reduce the ISI. Similarly, this technique can be leveraged to remove ISI while transmitting 3 or more CIDs.

Benefits of iPWM Encoding:

The timing diagram of the proposed iPWM encoding and comparison with the Manchester/PWM encoding is shown in Fig. 3. In case of Manchester encoding (Fig. 3(a)), bit one is represented by a signal, which stays high for 50% of the period and low for the remaining 50%. Bit zero is represented by a signal, which is low 50% of the period and then goes high. In PWM encoding, the time for which the signal stays high and low can be varied from 0% to 50% depending on the channel loss. In the presence of CIDs, the Manchester/PWM encoding generate narrow pulses, which must be transmitted through pre-driver and output driver to be precisely reproduced at the channel. These narrow pulses necessitate very wide bandwidth in the high-speed data path, resulting in poor energy efficiency and difficulty in scaling the Manchester/PWM encoding to higher data rates.

Figure 3 : (a) Manchester/PWM encoded data and problem of narrow pulse width generation. (b) Timing diagram of the proposed iPWM encoding for post-cursor and pre-cursor equalization.

The proposed iPWM encoding avoids inserting narrow pulses and instead reduces the pulse width of CIDs to achieve equalization, as shown in Fig. 3(b). Post cursor ISI is reduced by reducing the trailing edges of CIDs, while the pre-cursor ISI can be reduced by reducing the leading edges of CIDs.

It can observe from Fig. 3(b) that the number of transitions in the iPWM encoded data is same as that of NRZ data, and therefore, the bandwidth requirement on the high-speed data path of the output driver, in case of the iPWM encoding technique, is the same as that of the NRZ encoding. This helps in increasing the data rates of iPWM encoded data to 56Gb/s and beyond, without exponentially increasing the switching power of the transmitter.

Furthermore, conventional Manchester encoding technique has a lower limit on the minimum pulse width that can be transmitted because of the bandwidth limitation on the data path, which often results in over equalizing of a low-loss channel. When over equalization occurs, ISI is added instead of being subtracted, resulting in incorrect detection at the receiver, and consequently, higher bit error rate. The proposed iPWM encoding can change the pulse width of CIDs with very high precision (1ps precision or better can be easily achieved in 65nm CMOS), which helps to equalize a wide range of channel loss. Since iPWM encoding is done before the pre-driver, the output driver can be implemented as an unsegmented source series terminated driver. This reduces the signaling and switching power of the transmitter, which makes the proposed iPWM an energy efficient equalization scheme. Moreover, the proposed iPWM also helps to decouple the 50 termination tuning with the encoding coefficient tuning in source series terminated output driver. In summary, the proposed iPWM (1) does not generate narrow pulses, (2) can equalize a wide range of loss, (3) reduces transmitter signaling and switching power, (4) decouples 50 termination resistor tuning from coefficient tuning, and (5) uses technology scalable encoding architecture.

ADVANTAGES:

  • Number of Channels increases
  • Data rate per channel will increases
  • Less area and power consumptions

 

 

REFERENCES:

[1] T. Anand. Wireline Link Performance Survey. Accessed: Jan. 2018. [Online]. Available: https://web.engr.oregonstate.edu/~anandt/linksurvey

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