A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter with Cycle-Controlled DPWM

A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter with Cycle-Controlled DPWM

ABSTRACT:

This paper presents a wide-voltage-range, fast-transient all-digital buck converter using a high-resolution digital pulsewidth modulator (DPWM). The converter employs the multithreshold-voltage band-control technique to shorten its transient response. The DPWM uses an all-digital delay-locked loop (ADDLL) to control its cycle. The usage of ADDLL leads to the DPWM possessing a small area while maintaining high cycle resolution. Moreover, the proposed ADDLL-based cycle controlled DPWM can achieve synchronization between its input and output. This decreases the loop delay of the proposed converter so that the system is easy to be stabilized. The prototype chips of both the ADDLL-based cycle-controlled DPWM and the all-digital buck converter are fabricated in 0.35-µm CMOS process. Measurement results of the cycle controlled DPWM show that the duty cycle of its output is adjustable from 1% to 99% in a 0.78% increment per step when operating at 1 MHz. The measured transition time of the all-digital buck converter is < 3.5 µs when the load current changes from 50 to 500 mA, and vice versa. The proposed architecture of this paper the area and power consumption are analysis using tanner tools.

PROJECT OUTPUT VIDEO: (Click the below link to see the project output video):

EXISTING SYSTEM:

A conventional buck converter is realized in analog circuits, and it requires lots of passive components in its compensator to stabilize the loop. Compared with the analog realizations, the digital buck converters are not only less sensitive to the process, voltage, and temperature (PVT) variations but also much easier to be integrated into a system-on-a-chip solution. Furthermore, benefiting from the digital nature, it is much easier for engineers to design process independent all-digital buck converters than to design their analog counterparts. All the above features make the all-digital buck converters attractive in power management applications.

Fig. 1 shows the conventional digital-controlled buck converter. It consists of an analog-to-digital converter (ADC), a digital compensator, a digital pulsewidth modulator (DPWM), two power transistors, and an LC output filter. Conventionally, the digital-controlled buck converters are not popular in power management because of the following reasons.

Fig. 1. Conventional digital-controlled buck converters.

  1. The high-resolution ADC in a buck converter consumes significant power and occupies a large chip area. Meanwhile, an ADC is extremely sensitive to the supply voltage variation. Furthermore, designing a high-resolution ADC takes intensive design efforts.
  2. The digital compensator is usually realized by a lookup table circuit, which also occupies a large chip area.
  3. To realize a high-resolution DPWM, lots of delay elements and multiplexers (MUXs) are required. This results in a considerable increase of the chip area. On the other hand, the latencies for generating different duty-cycle outputs are different. It is difficult to keep the buck converter stable for such a wide range of latency.
  4. Limit cycle oscillations (LCOs) due to finite precision of the ADC and/or finite precision of the DPWM may occur in the digital-controlled buck converter. This not only worsens the ripples in its regulated output, but also limits the tunable output range of the buck converter.
  5. The response time of the digital-controlled buck converter highly depends on the operating frequency of the digital controller and the converter itself. To fulfill the fast-transient requirement for a load change, the operating frequency of the digital controller and the converter itself should be as high as possible. Unfortunately, increasing the operating frequency of the converter worsens the switching loss dramatically and lowers the converter’s conversion efficiency.

DISADVANTAGES:

  • Duty cycle range is less
  • Power management is not better

PROPOSED SYSTEM:

Fig. 2. Simplified architecture of the fast-transient wide-voltage-range, all-digital buck converter.

Fig. 2 shows the simplified architecture of the proposed fast transient all-digital buck converter. It consists of two power transistors, a MUX, a linear control circuit, a MTVB control circuit, a divider, a lock detector (LD), a dead-time circuit with buffers, and an LC output filter. Two clock signals, CLK and CLK Div, are used for the linear control circuit to lower the power consumption. To shorten the response time of the buck converter, the feedback control of the proposed buck converter operates in two modes, the nonlinear control mode and the linear control mode, according to the outputs of the MTVB control circuits. If the regulated output is outside the voltage range delimited by [VL, VH], the buck converter operates in the nonlinear control mode by selecting the comparison result of the MTVB control circuit (Comp) through the MUX to modulate the power transistor.

Fig. 3. Flowchart of the proposed all-digital buck converter

Fig. 3 shows the flowchart of the control mechanism of the proposed buck converter. The linear control mechanism of the proposed all-digital buck converter employs the pulse width modulation (PWM) due to its high conversion efficiency during the heavy-load period in which the PWM controller introduces smaller ripples to the regulated output than any other control technique does.

Fig. 4. Block diagram of the linear control circuit.

Fig. 4 shows the block diagram of the linear control circuit. It consists of a 7-bit up/down counter, a cycle-controlled DPWM, and a three-input AND gate. To reduce the power consumption in the up/down counter, the operating frequency of the counter is chosen lower than the operating frequency of the DPWM. The duty cycle of the cycle-controlled DPWMs output is adjustable depending on the logic level of Comp at every rising edge of CLK. If Comp is logic HIGH, the output duty cycle of the DPWM increases. Otherwise, the output duty cycle of the DPWM decreases.

MTVB Control Circuit

Fig. 5. Schematic of the MTVB control circuit and its truth table.

Fig. 5 shows the schematic of the MTVB control circuit and its truth table. It consists of three hysteresis comparators and one NAND gate. The hysteresis comparators are utilized here to prevent the comparison results from being affected by the unexpected high-frequency spikes of Vout. The first comparator, Comp1, compares the regulated output, Vout, with the target voltage, VRef, and generates a binary output, Comp. The second and the third comparators, Comp2 and Comp3, are used to detect whether VH > Vout > VL or not.

Cycle-Controlled DPWM

Fig. 6(a) shows the simplified architecture of the DPWM. A pulse generator is utilized to generate a fixed duty cycle output, CLKPULSE. This prevents both inputs of the NOR-based set-reset flipflop (SRFF) from being set to logic HIGH at the same time. The rising edge of CLKPULSE sets the SRFF to logic HIGH. Meanwhile, CLKPULSE also enters the cycle-controlled delay line (CCDL). After passing through the delay line, the rising edge of its delayed version, CLKR, resets the SRFF to logic LOW. The schematic of the CCDL and its timing diagram are shown in Fig. 6(b). It consists of an MUX, a deMUX (DEMUX), a one-shot circuit, a digital-controlled delay line (DCDL), an inverter, a 7-bit counter, and a 7-bit comparator.

Fig. 6. (a) Simplified architecture of the DPWM. (b) Schematic of the CCDL and its timing diagram.

Fig. 7 shows the detail schematic of the cycle-controlled DPWM and its corresponding timing diagram. The proposed cyclecontrolled DPWM consists of a start-controlled circuit [17], one pulse generator [18], a MUX, a DEMUX, a DCDL [19], a 7-bit counter, a 7-bit successive-approximationregister (SAR) circuit [20], a bit comparator, an SRFF, a DFF, a phase detector (PD), and some control logics as shown in Fig. 7(a). The proposed DPWM has two operation modes, namely, the ADDLL mode and the DPWM mode, respectively. The timing diagram of the DPWM is shown in Fig. 7(b).

Fig. 7. (a) Proposed cycle-controlled DPWM. (b) Timing diagram of the cycle-controlled DPWM.

Lock Detector

To avoid dithering of the comparison results between VRef and Vout due to the finite resolution of digital circuits, an LD is employed to detect dithering of Comp, the comparison result of the MTVB circuit.

ADVANTAGES:

  • wide duty cycle control
  • regulated output’s tunable range wide

SOFTWARE IMPLEMENTATION:

  • Tanner tools
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