Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application

Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application

 

ABSTRACT:

A conditional-boosting flip-flop is proposed for ultra-low voltage application where the supply voltage is scaled down to the near-threshold region. The proposed flip-flop adopts voltage boosting to provide low latency with reduced performance variability in the near threshold voltage region. It also adopts conditional capture to minimize the switching power consumption by eliminating redundant boosting operations. Experimental results in a 65-nm CMOS process indicated that the proposed flip-flop provided up to 72% lower latency with 75% less performance variability due to process variation, and up to 67% improved energy-delay product at 25% switching activity compared with conventional pre charged differential flip-flops. The proposed architecture of this paper is analysis the logic size, area and power consumption using tanner tool.

EXISTING SYSTEM:

Capacitive boosting can be a solution to overcome theproblems caused by aggressive voltage scaling. It allows the gatesource voltage of some MOS transistors to be boosted above thesupply voltage or below the ground.The enhanced driving capabilityof transistors thus obtained can reduce the latency and its sensitivity to process variations. The bootstrapped CMOS driver presented in [8] relies on this technique to drive heavy capacitive loads with substantially reduced latency. However, since it is a static driver, every input transition causes the bootstrapping operation. So, if some of the transitions are redundant, a large amount of redundant power consumption may occur. The conditional-bootstrapping latched CMOS driver [9] proposes the concept of conditional bootstrapping to eliminate the redundant power consumption. As it is a latched driver, it can allow boosting only when the input and output logic values are different, resulting in no redundant boosting and improved energy efficiency, especially at low switching activity. Recently, a differential CMOS logic family adapting the boosting technique has also been proposed for fast operation at the near-threshold voltage region.

DISADVANTAGES:

  • Low speed
  • Less performance

PROPOSED SYSTEM:

For incorporating the conditional boosting into a pre charged differential flip-flop, four different scenarios regarding input data capture should be considered, which are determined by the logic states of the input and output. These scenarios are as follows:

  • For a low output data, a high input data should trigger boosting for a fast capture of incoming data;
  • For a low output data, a low input data should trigger no boosting since the input need not be captured;
  • For a high output data, a low input data should trigger boosting for a fast capture of incoming data;
  • For a high output data, a high input data should trigger no boosting.

These scenarios can be embodied into a circuit topology using a single boosting capacitor by a combination of two operation principles. One is that the voltage presetting for the terminals of the boosting capacitor must be determined by the data stored at the output (so-called output-dependent presetting). The other principle is that boosting operations must be conditional to the input data given to the flip-flop (so called input-dependent boosting). The conceptual circuit diagrams for supporting these principles are shown in Fig. 1.To support the output-dependent presetting, the preset voltages of capacitor terminals N and NB are made to be determined by outputs Qand QB as shown in Fig. 1(a). If Q and QB are low and high, N and NB are preset to be low and high [left diagram in Fig. 1(a)], and if Q and QB are high and low, N and NB are preset to be high and low [right diagram in Fig. 1(a)], respectively. To support the input dependent boosting, the non-inverting input (D) is coupled to NB through an nMOS transistor and the inverting input (DB) is coupled to N through another nMOS transistor, as shown in Fig. 1(b). Then, as one case in which a low data is stored in the flip-flop, resulting in the capacitor presetting given in the left diagram in Fig. 1(a),a high input allows NB to be pulled down to the ground, letting N being boosted toward–VDD due to capacitive coupling [upperleft diagram in Fig. 1(b)]. Meanwhile, a low input allows N to be connected to the ground, but since the node is already preset to VSS, there is no voltage change at NB, resulting in no boosting [lower left diagram in Fig. 1(b)]. As the other case in which a high data is stored in the flip-flop, resulting in the capacitor presetting given in right diagram in Fig. 1(a), a low input allows N to be pulled down to the ground, letting NB being boosted toward –VDD due to capacitive coupling [lower right diagram in Fig. 1(b)].

Figure 1: Conceptual circuit diagrams for (a) output data-dependent presetting

Meanwhile, a high input allows NB to be connected to the ground, but since the node is already preset to VSS, there is no voltage change at N, resulting in no boosting [upper right diagram in Fig. 1(b)].Table I summarizes these operations for easier understanding. With these operations, any redundant boosting can be eliminated, resulting in a significant power reduction, especially at low switching activity.

Table 1: DATA-DEPENDENTPRESETTING ANDBOOSTING

Circuit Implementation:

The structure of the proposed conditional-boosting flip-flop (CBFF) based on the concepts described in the previous section is shown in Fig. 2. It consists of a conditional-boosting differential stage, a symmetric latch, and an explicit brief pulse generator. In the conditional boosting differential stage shown in Fig. 2(a), MP5/MP6/MP7and MN8/MN9 are used to perform the output-dependent presetting, whereas MN5/MN6/MN7 with boosting capacitor CBOOT are used to perform the input-dependent boosting. MP8–MP13 andMN10–MN15 constitute the symmetric latch, as shown in Fig. 2(b).Some transistors in the differential stage are driven by a brief pulsed signal PS generated by a novel explicit pulse generator shown in Fig. 2(c). Unlike conventional pulse generators, the proposed pulse generator has no pMOS keeper, resulting in higher speed and lower power due to no signal fighting during the pull-down of PSB. The role of the keeper to maintain a high logic value of PSB is done by MP1added in parallel with MN1, which also helps a fast pull-down of PSB. At the rising edge of CLK, PSB is rapidly discharged by MN1, MP1, and I1, letting PS high. After the latency of I2 and I3,PSB is charged by MP2, and so PS returns to low, resulting in a brief positive pulseat PS whose width is determined by the latency of I2 and I3. When CLKis low, PSB is maintained high by MP1, although MP2 is OFF. According to our evaluation, the energy reduction is up to 9% for the same slew rate and pulse width.

Figure 2: Proposed CBFF. (a) Conditional-boosting differential stage. (b) Symmetric latch. (c) Explicit brief pulse generator.

ADVANTAGES:

  • High speed
  • High performance

SOFTWARE IMPLEMENTATION:

  • Tanner EDA
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