An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers

An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers

 

ABSTRACT:

An add-on type real-time jitter tolerance enhancer (JTE) is presented in this paper. The proposed JTE can improve high-frequency jitter tolerance (JTOL) by using a real-time phase alignment scheme. A mathematical analysis for an advanced bit error rate (BER) prediction method is also introduced. The proposed circuit is applicable to various types of receivers, such as referenceless receivers, receivers with a reference clock source, and source-synchronous receivers. The referenceless receiver with the proposed JTE achieved an out-of-band JTOL of 0.71 UIpp at 100 MHz with < 10−12 BER. Total core areas of the receiver and JTE are 0.19 and 0.07 mm2 in a 0.13-µm CMOS process, respectively. The power consumption of the receiver is 38 mW at 5.4 Gbit/s, and the JTE dissipates 22 mW. The proposed architecture of this paper the area and power consumption are analysis using tanner tools.

EXISTING SYSTEM:

Several JTOL-enhancing techniques have been reported in the literature. A gated-digital-controlled oscillator (GDCO)-based clock and data recovery (CDR) circuit were used to enhance JTOL by cascading the high frequency and low-frequency jitter tracking bandwidth (JTB) loops. The semi blind oversampling CDR uses the elastic FIFO to enhance the low-frequency JTOL. A clock-forwarded receiver with injection-locked oscillator (ILO) enhances the JTOL by increasing the JTB. However, the GDCO-based CDR requires an additional frequency calibration circuit in order to minimize its inherent frequency offset. Both the oversampling method and the FIFO incur a large power penalty and the very wide JTB increases unwanted clock jitter. The ILO also requires an additional frequency calibration circuit and a considerably high JTB makes the receiver vulnerable to the noise. Moreover, previous architectures presented in deal with methods to track the input data.

 

DISADVANTAGES:

  • Jitter is produced

 

PROPOSED SYSTEM:

The overall architecture of the receiver with the proposed JTE is shown in Fig. 1. The receiver is composed of an equalizer (EQ), CDR [10], and JTE. The EQ employs an established EQ filter and compensates for the ISI of the input data. The CDR receives the EQ’s output, EQ_OUT, through the 4 delay line. These delay cells help to align the CLKALIGN at the center of the JTE’s delay line, so that the JTE can realign the input data with the maximum alignment range. The CDR operates as follows. First, the frequency detector sets up the VCO’s operating frequency with a random data pattern. Second, the phase detector and charge pump (CP) align CLKSAMPLING to the center of the 4-delayed EQ_OUT. Finally, the recovered clocks (CLK_OUT, CLKSAMPLING, and CLKALIGN) generated by the VCO, and EQ_OUT, are delivered to the JTE. The CDR shown in Fig. 1 is a reference for the JTOL performance comparison.

Fig. 1. Overall block diagram of the receiver with the proposed JTE.

The bottom of Fig. 1 shows a block diagram of the proposed JTE. Unlike the feedback architecture of the phase-aligner.

Equalizer and Delay Line

Fig. 2 shows a detailed block diagram of the EQ and the delay line. The EQ is composed of a continuous time linear EQ (CTLE), limiter, and current mode logic (CML)- to-CMOS converter, as shown in Fig. 2(a). The CML-toCMOS converter output, EQ_OUT, is a full swing signal, which means the JTE is insensitive to the input swing level. However, if the channel loss is too high to maintain the full swing, then the uncompensated ISI jitter from the EQ will be directly inserted to the JTE. In other words, if there are some residual ISI not cancelled by the CTLE, then that ISI will appear at the delay line output and it can be amplified at the worst corner.

Fig. 2. Block diagram of (a) EQ, (b) one delay cell, and (c) schematic of one inverter cell.

Edge Detector

Fig. 3 shows a block diagram of the proposed edge detector (ED). The ED consists of a dual-edge-triggered flip-flop (dual FF), XOR gates, and a selection code holder (SCH).

Fig. 3. Block diagram of the proposed ED.

Phase Selector

After the ED produces the selection code, the phase selector (PS) selects the multiphase data (2Δ, 4 Δ, and 6 Δ). A block diagram of the PS is shown in Fig. 4.

Fig. 4. Block diagram of the PS.

 

ADVANTAGES:

  • reducing the data jitter

 

SOFTWARE IMPLEMENTATION:

  • Tanner tools
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