A 30-W 90% Efficiency Dual-Mode Controlled DC–DC Controller With Power Over Ethernet Interface for Power Device
A dual-mode controlled dc–dc controller with power over Ethernet (PoE) interface for power device (PD) is presented that is designed to support drawing power either from an Ethernet cable or from an external auxiliary supply support (ASS). PoE interface supports all the functions that comply with the IEEE802.3af/at standard. Based on band gap reference structure, a detection comparator is provided to detect input voltage without extra voltage reference. Using a low offset voltage amplifier, a low loss current-limiting technique is proposed to achieve a high precision current-limit point. Based on a high-speed comparator and two timing capacitors, an oscillator (OSC) is implemented for better accuracy, and provides the maximum duty cycle (Dmax) and external frequency synchronization. The chip is fabricated in a 0.5-µm 65 V BCD process and occupies a die size (with pads) of 1.79 × 2.76 mm2. The experimental results are measured for an active clamp forward converter with a wide range of dc input voltages from 33 to 57 V, an output voltage of 12 V, and an output power of 30 W. The chip achieves peak power efficiency of 90% and 90.63% on DC and ASS, respectively. The load regulation at different input voltages can be measured to be within ±0.11%. Measurements further show that the peak-to-peak ripple voltage of the chip is 161 mV and the recovery time is less than 1.2 ms for the 2-A load step.
RECENTLY, the power over Ethernet (PoE) system has been one of the most popular topics, and it has wide ranging prospects in the global networking market. The PoE represents a standardized system to transfer data along with electrical power on Ethernet cabling without any extra power cable or adapter, greatly reducing the overall installation and maintenance cost. Due to the advantages of saving space, flexibility, and cost in application, the PoE system can be widely applied to video and Voice over Internet Protocol telephones, RFID readers, multiband access points, security cameras, and so on. With the development of new application areas and markets for the PoE system, research and design of the PoE system has been proposed to satisfy more demanding applications. Meanwhile, the PoE system needs to be highly stable in its various applications, due to high operating voltage and high power, which increases the need for further research and design of the PoE system.
Since industrial products require more power and higher conversion efficiency , it became necessary to deliver a higher power level. The IEEE802.3af standard was replaced by IEEE802.3at which supports power levels up to 25.5 W and increases the operating current from 350 to 720 mA. According to the IEEE802.3af/at, devices compliant with IEEE802.3af and IEEE802.3at are referred to as type 1 and type 2 devices, respectively. A typical PoE system consists of power sourcing equipment (PSE) and a power device (PD) . A typical example of the architecture of the PoE system is shown in Fig. 1. From Fig. 1, the data are transferred through CAT-5 network cable to the application, while the PSE injects power into the cable. The PD therefore receives both data and power via the cable. In order to ensure that the desired power can be transmitted safely and smoothly over an Ethernet cable, both the PSE and PD need to have appropriate power management ICs to manage and control the entire power transmission process. The power management ICs of the PD include a PoE interface and dc–dc controller and are the interface between the Ethernet cable and IP devices. The PoE interface is responsible for the communication with PSE and supports all the functions that comply with the IEEE802.3af/at standard. Meanwhile, the dc–dc controller employs voltage conversion to regulate the output voltage to the desired level.
- More Power Consumption
- Technology used 500nm.
Due to security and the cost of the system, flyback and forward converters are normally applied in PoE systems. The prototype converter targets high-efficiency conversion at all load conditions supporting synchronous flyback topology and active clamp forward (ACF) topology. The ACF topology is clearly described and analyzed  – , and thus its related content will not be described with detailed theory analysis in this paper. The system diagram of the proposed high-efficiency converter is shown in Fig. 2. It mainly consists of bypass capacitor C1, transient suppressor diodes D0 and D1, type- π filter, main MOSFET Q1, auxiliary MOSFET Q2, lowside active clamp (LSAC) circuit, amplifier U1, optocoupler U2, synchronous rectifiers SR1 and SR2, type-II compensation network, output capacitor CO , output inductor L O , type-2 PSE indicator, and control IC.
As shown in Fig. 2, the LSAC circuit is used to produce output voltage levels below SG. U1 and U2 provide output regulation feedback for a current mode control. The type-II compensator is used to achieve optimized loop bandwidth and fast transient responses. Type-2 PSE indicator can indicate that the connected PD is a type-2 PD. Through the DE and CL pins, the PoE detection signature and the class current are provided, respectively.
The blanking time, dead time, and switching frequency are programmed through the BK, DT, and FS pins, respectively. The secondary-side regulation scheme is adopted to monitor the output voltage, and the optocoupler feedback is transfer to the FB pin to generate the pulse width-modulated (PWM) signal. VH and VL pins are the bias rail and the internal high-voltage regulator output, respectively. PG and VSS pins are two-event classification indicator and the system low potential input, respectively. The GND, VOUT, and SG pins are the power ground of the driver, the drain of NS3, and the analog ground of the dc–dc controller, respectively (they are tied together on the circuit board). In addition, SG pin is the floating analog ground. The chip integrates a hotswap MOSFET to isolate the grounds of the PoE interface and dc–dc controller . After startup, VOUT falls from VDD to nearly VSS as CIN is charged, and then the current of the chip is limited. This scheme deals with the problem of different grounds of PoE and dc–dc controller and limits the current of the chip.
- Less Power Consumption
- Technology used 130nm.