A 65-nm CMOS Constant Current Source with Reduced PVT Variation

A 65-nm CMOS Constant Current Source with Reduced PVT Variation



This paper presents a new nanometer-based low-power constant current reference that attains a small value in the total process–voltage–temperature variation. The circuit architecture is based on the embodiment of a process-tolerant bias current circuit and a scaled process-tracking bias voltage source for the dedicated temperature-compensated voltage to-current conversion in a pre regulator loop. Fabricated in a UMC 65-nm CMOS process, it consumes 7.18µWwitha1.4V supply. The measured results indicate that the current reference achieves an average temperature coefficient of 119 ppm/°C over 12 samples in a temperature range from−30 °C to 90 °C without any calibration. Besides, a low line sensitivity of 180 ppm/V is obtained. This paper offers a better sensitivity figure of merit with respect to the reported representative counterparts. The proposed architecture of this paper analysis the logic size, area and power consumption using Tanner tool.

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Oguey and Aebischer presented a self-biased topology by means of biasing a triode-biased nMOS transistor through a saturation-biased transistor in a circuit feedback loop for current generation. However, it has difficulty canceling the temperature effect arising from the matching between the mobility temperature exponent and the mobility degradation factor. Besides, the VTH mismatch issue between the tracking device pair will degrade the current accuracy. Due to the topology, the current reference suffers from poor line sensitivity (10%/V). All of these non ideal effects cause the accuracy of the reference current to deviate significantly from the process variations (∼±30%). Alternatively, a low-voltage, low-power MOSFET-only self-biased current source was reported. The temperature dependence could reach as high as 2500 ppm/°C over the operating range of −20 °C to 70 °C. To improve the temperature coefficient (T.C.), suggested second-order temperature compensation. Since both the reference current and its T.C.are process sensitive, unavoidable trimming is required to preserve the accuracy. Later, Bendali and Audet showed a reference circuit utilizing the zero T.C. point of the transistorto generate a constant output current. This relies on the temperature compensation concept using mutual temperature compensation between the carrier mobility and the threshold voltage. Following a similar technique, Uenoet al. realized the current reference with an improved T.C. of46 ppm/°C. Although a low line sensitivity is achieved, it may not be adequate if the circuit is designed using nanometer technology. At this juncture, the output current, which is obtained from the saturation-based transistor to serve as a VI converter, is sensitive to the offset of the driving op-amp, thus increasing the process sensitivity. In another design, a current reference was generated by means of a constant overdrive voltage. However, the line sensitivity becomes a major concern because the supply voltage needs to be well controlled. Turning to the current summing design technique, the power consumption is generally high because of the circuit’s complexity. Although the floating-gate transistor-based current reference offers a precise current, it is expensive in the trimming method. The same is true of the low T.C. current reference, which depends upon a low T.C precision-trimmed voltage reference at the expense of drawing extra power. It is of particular note that these reported designs are implemented using 0.18-μm CMOS technology or above. As the technology is further scaled down to sub100 nm, the performance of current references will be degraded by the process–voltage–temperature (PVT) variations. This stems from the fact that the process variations arising from the lithography imperfections and uncontrollable factors such as random dopant fluctuations, the well proximity effect, and layout-dependent stress variation impose challenges for robust circuit designs. In addition, the MOS transistors suffer from a high current leakage level. The temperature-fluctuation-induced variation in the carrier mobility becomes significantly higher for MOSFET devices in the exemplary 65-nm CMOS technology than in the 0.18-μm technology. Finally, the short-channel effect (SCE) contributes another factor that limits the circuit performance in advanced nanometer technology. In brief, the lower the channel length in a technology, the more difficult it is to achieve a stable reference design because of the relatively poor output characteristic of long channel transistors compared with those with higher channel lengths in technologies. As a consequence, the design in a 65-nm process turns out to be more challenging than that in other processes (>65 nm) even when transistors with larger than the minimum size are used.


  • Sensitivity is low


Table I summarizes the acronyms and nomenclature adopted in this paper. The constant current generation is devised from a process-tolerant temperature-compensated VI converter. It aims at establishing a constant VTH0 reference compensation voltage having a first-order T.C. with reduced process sensitivity in series with another auxiliary compensation voltage having a second-order T.C. with low process sensitivity. The combined temperature characteristic will match the corresponding linear T.C. and nonlinear T.C. of the integrated resistor in the VI converter. The outcome leads to a constant current reference with reduced PVT variation. The operation principle of this proposed circuit is illustrated in Fig. 1.

Figure 1: Operation principle of the proposedIREFcircuit with the temperature characteristic of (a)VGS(T),(b)VAux_Comp(T),(c)VR_Comp(T),(d)RO(T), and (e)IREF

A process-tolerant bias current (IPTol) and a process tracking voltage (VPTrack) are generated through the IPTol and VPTrack bias circuits in self-biasing topology. When a scaled IPTol is injected into a MOSFET transistor, it will generate a gate–source voltage VGS(T) with a first order negative T.C., as shown in Fig. 1(a). Fig. 1(c) depicts the target reference compensation voltage VR_Comp(T) that is formed by summing the nonlinear auxiliary compensation voltage VAux_Comp(T) in Fig. 1(b) with the gate–source voltage VGS(T). On the other hand, VAux_Comp(T) is synthesized from the current-to-voltage (IV) conversion in which the scaled IPTol is passed to an active resistor. The resistor realization is based on a scaled VP Track to bias the gate of the triode transistor. Since VR_Comp(T) exhibits a similar T.C. to the sense resistor RO(T)with the temperature characteristic shown in Fig. 1(d), the final output current IREF can be made temperature independent over the operating temperature range as illustrated in Fig. 1(e).

Implementation of proposed current reference:

The current reference depicted in Fig. 2 consists of a pre regulator, a process-tolerant current bias circuit with an embedded process-tracking voltage bias circuit, and a temperature-compensated VI converter. For simplicity, the capacitive startup circuit and the biasing circuit are not shown. The pre regulator loop, which has been reported in a nanometer-based MOSFETVTH measurement circuit, is used to provide good line sensitivity. Referring to Fig. 2,when the op-amp is employed in the bias current circuit, the drain voltages at nodes N1 and N2 are close to each other. This establishes identical currents flowing throughM1 and M2, which are biased in the sub-threshold region. On the other hand,MR1 operates in the triode region as an active resistor. It is self-biased by VPTrack, which is generated from M8 in the saturation region. This turns out to be a process-tolerant active resistor RMR1. As such, the current IPTol flowing throughM1 orM2 becomes process tolerant.

Figure 2: Schematic of the proposed constant current reference circuit.


  • Sensitivity is high


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