### A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using Dynamically Biased Op Amp Sharing

__A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using Dynamically Biased Op Amp Sharing__

__A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using Dynamically Biased Op Amp Sharing__

__ABSTRACT:__

A 2–2 cascaded switched-capacitor sigma-delta modulator is presented for design of low-voltage, low-power, broadband analog-to-digital conversion. To reduce power dissipation in both analog and digital circuits and ensure low-voltage operation, a half-sample delayed-input feed forward architecture is employed in combination with 4-bit quantization, which results in reduced integrator output swings and relaxed timing constraint in the feedback path. The integrator power is further reduced by sharing an op amp in the two integrators in each stage and periodically changing the op amp bias condition between a high-current and a low-current mode using a fast low-power high-precision charge pump circuit. Implemented in a 0.18-μm CMOS technology, the experimental prototype achieves a 92-dB dynamic range, a 91-dB peak signal-to-noise ratio, and an 84-dB peak signal-to-noise plus distortion ratio, respectively for a signal bandwidth of 1.25 MHz Operated at a 40-MHz sampling rate, the modulator dissipates 24.3 mW from a 1 V supply The proposed architecture of this paper analysis the logic size, area and power consumption using Tanner tool.

__EXISTING SYSTEM:__

Oversampling ADCs based on use of sigma–delta modulation offer a means of overcoming the constraints imposed on analog circuit performance by scaling of the technology by exchanging resolution in time for that in amplitude. As a result, a high-precision ADC output can be generated by using back-end digital decimation filtering. However, use of oversampling sigma delta ADCs is typically limited to low-bandwidth applications, such as digital audio and sensor systems, due to the high oversampling ratio required to achieve good conversion accuracy. Meanwhile, sigma delta modulators operating at relatively low oversampling ratios have been shown to be effective means of implementing high-performance ADCs for a signal bandwidth of several megahertz. Design techniques for low voltage low-power operation have also been introduced from an architecture view point, such as an input feed forward and a one-sample delayed input feed forward modulator architecture, and a circuit design view point, such as a double sampling, an inverter or zero-crossing-based stage implementation, an op amp switching, and an op amp sharing.

A megahertz-bandwidth 2–2 cascaded sigma delta modulator is presented, which employs a fast dynamic biasing to reduce power in an integrator op amp that is shared by two integrators. A half-sample delayed-input feed forward architecture is used for implementation of each stage in the2–2 cascaded modulator. This approach, in combination with 4-bit quantization, reduces the integrator output swing and relaxes the timing constraints imposed on the feedback path without requiring any additional circuitry to implement the added delay. As a result, low-voltage low-power operation is enabled for the integrators, the quantizer, and the feedback digital-to-analog converter (DAC). In order to further reduce the integrator power, the two integrators in each stage share a single op amp, and the bias condition of the shared op amp is periodically changed between a high-current mode and a low-current mode to exploit op amp power scaling in discrete-time (DT) integrators. The dynamic biasing of the op amp is performed by a fast low-power charge pump circuit, which precisely changes the op amp bias during the non-overlapping clock periods of the two-phase clocks.

__DISADVANTAGES____:__

- Area coverage is high
- Power consumption is high

__PROPOSED SYSTEM:__

Stage Architecture:

Three different modulator architectures, the distributed feedback architecture, the input feed forward architecture, and the half-sample delayed-input feedforward architecture, are compared in this section based on the magnitude of the first integrator output swing. The reason for this basis is that the integrator output swing greatly affects the integrator power, and the first integrator is one of the most power-hungry blocks in a deta modulator. To simplify the comparison and ensure the modulator stability, only second order modulators are considered.

Figure 1: Second-order modulator with (a) distributed feedback architecture, (b) input feed forward architecture, and (c) half-sample delayed-input feed forward architecture

In the distributed feedback architecture shown in Fig. 1(a), the first integrator processes the modulator input along with the quantization error. This, in turn, results in a very large integrator output swing as the input amplitude approaches full-scale. In contrast, the integrators in the input feed forward architecture in Fig. 1(b) process only the quatization error, and thus, the integrator output swings are significantly reduced if multi-bit quantization is employed. In the half-sample delayed-input feed forward architecture in Fig. 1(c), the signal components at the first and second integrator outputs are not completely removed. However, since they are attenuated by a second-order and a first-order difference at the first integrator and second integrator outputs, respectively, the integrator output swings are very small, regardless of the modulator input if the oversampling ratio is not too low.

Behavioral simulations were performed on the magnitude of the first integrator output with respect to the modulator input power. In these simulations, quantization resolution was 4 bit, and the input frequency was at the edge of the signal bandwidth for an oversampling ratio of 16. The choice of the band-edge input frequency is to reflect the worst case scenario in Fig. 1(c), where a signal transfer function (STF) has a high-pass characteristic. All integrators and quantizers were assumed to be ideal. As shown in Fig. 2, the first integrat or output swing in Fig. 1(a) grows proportionally as the input power increases, whereas those in Fig. 1(b) and (c) remain nearly constant and small. This reduced integrator outputswing results in less nonlinear distortion in the integrator, and thus relaxes the dc gain and the speed required for the integrator op amp.

Op Amp Sharing:

Power and area of DT, multistage, op amp-based analog circuits can be reduced by means of op amp sharing. In a pipelined ADC, each stage op amp is reset during one of the two clock phases and transfers charge during the other clock phase. Therefore, an op amp can be shared by either adjacent stages or distant stages, with charge transfer occurring at the opposite clock phase.

In contrast, the op amps in a DT switched-capacitor sigma-delta modulator are always in a closed-loop configuration formed through integration capacitors. Typically, an integrator op amp transfers and integrates charge during one clock phase and drives the sampling capacitor in the following stage during the other clock phase. However, if a sigma-delta modulator is to be implemented using half-sample delayed integrators, as shown in Fig. 1(c), the integrator op amp integrates charge and drives the subsequent circuitry at the same time. Then, the op amp can be turned OFF in its sampling phase, or it can be shared by two integrators by alternately disconnecting integration capacitors from the op amp.

Figure 2: Second-order sigma-delta modulator with a shared op amp with two input pairs

To avoid this, in this paper, an op amp with two distinct input pairs is used for integrator op amps. A single-end edversion of the second-order stage implementation is shown in Fig.2, where 1-bit quantization is assumed for simplicity. The two op amp inputs are alternately turned ON and OFF, and the charges on the integration capacitors CI1 and CI2are preserved by correspondingly turning OFF series-connected switches SW1 and SW2 when an integrator is in its sampling phase. While the input signal is being sampled ontoCS1whenɸ1andɸ1d are high, the sampled charge onCS2is integrated to CI2.Whenɸ2 andɸ2d are high, the sampled charge onCS1 is integrated to CI1, and the integrated signal on CI1 is sampled ontoCS2. The added switches SW1and SW2 should be sized large enough in order not to slow the settling of the integrator.

**Dynamic Biasing:**

Although op amp sharing reduces the integrator power and area, the efficiency of power saving is not that high by itself. This is because, in a second-order sigma-delta modulator, for example, non-idealities introduced in the second integrator are greatly attenuated by the noise shaping provided by the loop filter in a feedback. Thus, smaller capacitors and less op amp power are needed in the second integrator compared with the first integrator. Consequently, power dissipation in op amp shared integrators can be further reduced by dynamically changing the op amp bias condition between a high-current mode for the first integrator and a low-current mode for the second integrator, as shown in Fig. 3. The key to this dynamic biasing is that the bias current change must be fast enough to be carried out during non-overlapping clock periods so as not to reduce the op amp settling time.

Figure 3: Dynamic biasing of an op amp.

Fig. 4 shows conventional dynamic biasing schemes. The output current of the bias circuit I OUT is changed by a current mirror [Fig. 4(a)] or a current steering quad [Fig. 4(b)].IOUT is then amplified by k times to establish the op ampbias current IOP. Despite the relatively simple structure, both circuits show a primary concern for the capability of fastop amp bias change. For the case of Fig. 4(a), it may take significant time to charge M3 gate when the switch control signal SW goes high, resulting in slow change in IOUT. Although this can be resolved by using a high-speed current steering quad as shown in Fig. 4(b), there still exists a charging and discharging node that can cause a substantial delay in the change of the op amp bias current. If the ratio of the IOUTto IOP, here denoted as k, islarge, IOP may change veryslowly due to a large capacitive load at node X. In contrast, if kis small, the power of the bias circuit itself will be comparable with the op amp power. This is particularly important in high-speed, sampled-data systems, where the constituent op amps dissipate fairly high power, and the devices in the op amps are typically large.

Figure 4: Conventional dynamic biasing using (a) switched current mirror and (b) current steering circuits.

__ADVANTAGES:__

- Area coverage is low
- Power consumption is low

__SOFTWARE IMPLEMENTATION:__

- Tanner tool