VLSI Projects 2017

VLSI IEEE Project Titles 2017 – 2018

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LOW POWER

A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging

Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture

Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding

A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption

Resource-Efficient SRAM-based Ternary Content Addressable Memory

Write-Amount-Aware Management Policies for STT-RAM Caches

Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA

High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder

High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map

Efficient Designs of Multi-ported Memory on FPGA

High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA

An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock

A 2.4–3.6-GHz Wideband Sub-harmonically Injection-Locked PLL with Adaptive Injection Timing Alignment Technique

Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares

Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm

A High-Efficiency 6.78-MHz Full Active Rectifier with Adaptive Time Delay Control for Wireless Power Transmission

Scalable Device Array for Statistical Characterization of BTI-Related Parameters

AREA EFFICIENT/ TIMING & DELAY REDUCTION

VLSI Design of 64bit × 64bit High Performance Multiplier with Redundant Binary Encoding

ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware

Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs

Efficient Soft Cancelation Decoder Architectures for Polar Codes

Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient Toeplitz Block Toeplitz Matrix–Vector Product Decomposition

Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication

FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers over GF (2m) and Their Applications in Trinomial Multipliers

Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Non-binary LDPC Codes Over Subfields

Antiwear Leveling Design for SSDs With Hybrid ECC Capability

Energy-Efficient VLSI Realization of Binary64 Division with Redundant Number Systems

Audio, Image and Video Processing

A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding

RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing

Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations

Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers

An FPGA-Based Hardware Accelerator for Traffic Sign Detection

Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations

Time-Encoded Values for Highly Efficient Stochastic Circuits

Design of Power and Area Efficient Approximate Multipliers

VERIFICATION

COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits

Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction

NETWORKING

Multicast-Aware High-Performance Wireless Network-on-Chip Architectures

VLSI – BACK END PROJECT – TANNER(nm) / HSPICE(nm) / DSCH3 – MICROWIND(um)

Temporarily Fine-Grained Sleep Technique for Near- and Sub-threshold Parallel Architectures

Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique

10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage

Delay Analysis for Current Mode Threshold Logic Gate Designs

Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications

Probability-Driven Multi-bit Flip-Flop Integration With Clock Gating

A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications

A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS

Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application

An All-MOSFET Sub-1-V Voltage Reference With a−51-dB PSR up to 60 MHz

A 65-nm CMOS Constant Current Source with Reduced PVT Variation

A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy

Preweighted Linearized VCO Analog-to-Digital Converter

A 100-mA, 99.11% Current Efficiency, 2-mVppRipple Digitally Controlled LDO with Active Ripple Suppression

Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template

On Micro-architectural Mechanisms for Cache Wear out Reduction

Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology

A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using Dynamically Biased Op Amp Sharing

A 0.45 V 147–375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures

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Contact: 09952649690 / Email: jpinfotechprojects@gmail.com