A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding

  • September 24, 2015
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A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding


The multiplication of wireless communication standards is introducing the need of flexible and reconfigurable multi standard baseband receivers. In this context, multiprocessor turbo decoders have been recently developed in order to support the increasing flexibility and throughput requirements of emerging applications. However, these solutions do not sufficiently address reconfiguration performance issues, which can be a limiting factor in the future. This brief presents the design of a reconfigurable multiprocessor architecture for turbo decoding achieving very fast reconfiguration without compromising the decoding performances.


A channel coding technique is typically associated to a variety of parameters and configuration options [frame size (FS), communication channel, signal-to-noise ratio, and so on]. Among channel coding techniques, turbo codes (TCs) are frequently adopted in the recent wireless standards to reach a very low bit error rate (BER). Furthermore, the high-throughput requirement of emerging services imposes the efficient exploitation of different parallelism levels of the underlying algorithms, such as subblock parallelism [1] or shuffled decoding [2] techniques. The introduction of contention-free interleavers in recent communication standards, such as WiMAX and LTE, enables high-throughput implementations presented in [3]–[8]. These architectures propose to use multiple Soft-Input Soft-Output (SISO) decoders to reach the high-throughput requirement of emerging and future standards. These turbo decoders offer certain degrees of flexibility to adapt for instance the number of SISO decoders, the TC mode, i.e., single binary TC (SBTC) or double binary TC (DBTC), or the FS. However, these efforts do not present any configuration infrastructures associated to these architectures in order to support fast and efficient dynamic configuration switches. Recently, application specific instructionset processor (ASIP) solutions have been investigated in order to offer architectures providing good tradeoffs in terms of flexibility, throughput, and power dissipation. In [9], a flexible and high-performance ASIP model for turbo decoding was proposed, which can be configured to support all SBTC and DBTC up to eight states. The architecture uses shuffled decoding with frame subblocking. Afterward, optimizations on the proposed ASIP, called DecASIP, have been added in [10]. Brehm et al. [11] introduced the FlexiTreP ASIP in a multi-ASIP architecture for turbo decoding to reach the 150 Mb/s throughput requirement of LTE. The FlexiTreP ASIP supports both SBTC and DBTC for various standards and it is configured through an interleaver memory, a program memory, and the dynamically reconfigurable channel code control.


In fact, previous works provide an efficient way to reach the high-performance requirement of emerging standards. However, the dynamic reconfiguration aspect of these platforms is superficially addressed. Among the few works that consider this issue, we can cite the recent architecture presented in [13], where solutions for the reconfiguration management of the NoC-based multiprocessor turbo/low-density parity-check (LDPC) decoder architecture presented in [14] were proposed. Up to 35 PEs and up to 8 configuration buses have been implemented. However, the proposed solution does not guarantee that the configuration process can be masked by the current decoding task. Then, stopping the current processing to configure the new configuration is unavoidable and leads to a decoding quality loss in terms of BER. To leverage these issues, this brief presents a novel dynamically reconfigurable turbo decoder providing an efficient and high-speed configuration process.



  • Modelsim 6.0
  • Xilinx 14.2


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