A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes

  • September 24, 2015
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A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes

ABSTRACT:

Radiation-induced soft errors are a major reliability concern for memories. To ensure that memory contents are not corrupted, single error correction double error detection (SEC-DED) codes are commonly used, however, in advanced technology nodes, soft errors frequently affect more than one memory bit. Since SEC-DED codes cannot correct multiple errors, they are often combined with interleaving. Interleaving, however, impacts memory design and performance and cannot always be used in small memories. This limitation has spurred interest in codes that can correct adjacent bit errors. In particular, several SEC-DED double adjacent error correction (SEC-DED-DAEC) codes have recently been proposed. Implementing DAEC has a cost as it

impacts the decoder complexity and delay. Another issue is that most of the new SEC-DED DAEC codes miscorrect some double nonadjacent bit errors. In this brief, a new class of SEC-DED-DAEC codes is derived from orthogonal latin squares codes. The new codes significantly reduce the decoding complexity and delay. In addition, the codes do not miscorrect any double nonadjacent bit errors. The main disadvantage of the new codes is that they require a larger number of parity check bits. Therefore, they can be useful when decoding delay or complexity is critical or when miscorrection of double nonadjacent bit errors is not acceptable. The proposed codes have been implemented in Hardware Description Language and compared with some of the existing SEC-DED-DAEC codes. The results confirm the reduction in decoder delay.

EXISTING SYSTEM:

Radiation-induced soft errors are a major concern for memory reliability [1]. To protect memories, error correction codes are commonly used [2]. Traditionally, single error correction double error detection (SEC-DED) codes have been used [3]. A SEC-DED code has a minimum Hamming distance of four and is able to correct single bit errors and detect double errors without miscorrection. This is important to avoid silent data corruption. SEC-DED codes are sufficient when errors affect only one bit, however, the percentage of soft errors affecting more than a single bit is increasing as technology scales [4]. For memories implemented in 40 nm and below, multiple bit errors are a significant percentage of errors and thus SEC-DED codes alone are no longer sufficient to protect memories. One option is to combine SEC-DED codes with interleaving [5]. Interleaving, places the bits that belong to the same logical word physically apart. As the errors caused by a radiation particle hit are physically close [6], this ensures that the errors affect at most one bit per logical word. Interleaving has an impact on the memory design. The routing is more complex and area and power consumption are increased. In addition, interleaving cannot always be used in small memories or register files nor can be practically applied to content addressable memories [7]. Another alternative is to use error correction codes that can correct adjacent bits. In many cases, directly adjacent bits account for over 90% of the observed multiple bit errors. Several codes have been recently proposed to this end. For example, a code that can correct double and triple adjacent errors for words of 16 bit was presented in [8]. In [9], a technique to design SEC-DED double adjacent error correction (SEC-DED-DAEC) codes was introduced.

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PROPOSED SYSTEM:

The proposed codes are derived from DEC OLS codes. Taking the parity check matrix in (1) as a starting point, the first step is to remove the m parity check bits that correspond to one of the Mi matrices. As an example, consider removing the M1 matrix from the matrix in Fig. 2 as shown in Fig. 3. The data bits that participated in each of the removed parity check equations will not share any parity check in the reduced matrix. This is a direct consequence from the property of OLS codes that any two data bits share (that is have a one in the same row in the H matrix) at most one parity check bit. This can be clearly observed in Fig. 2. In addition, those groups of m bits are marked as g1, g2, g3, and g4 in Fig. 3. For example, the first four data bits share the first parity check bit in the M1 matrix and form the first group g1. It can be observed that they do not share any other parity check bits. Therefore, when M1 is removed they do not share any parity check bit. The same occurs for the other groups of bits 5–8 (g2), 9-12 (g3), and 13–16 (g4). In the reduced matrix, each data bit participates in three parity checks. Therefore, if a majority vote is used to decode the bits, single and double errors can be corrected.

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SOFTWARE IMPLEMENTATION:

  • Modelsim 6.0
  • Xilinx 14.2

HARDWARE IMPLEMENTATION:

  • SPARTAN-III, SPARTAN-VI
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