40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface

  • September 24, 2015
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40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface

ABSTRACT:

This paper explores the use of transformer-coupled (TC) technique for the 2:1 MUX and the 1:2 DEMUX to serialize-and-deserialize (SerDes) high-speed data sequence. The widely used current-mode logic (CML) designs of latch and multiplexer/demultiplexer (MUX/DEMUX) are replaced by the proposed TC approach to allow the more headroom and to lower the power consumption. Through the stacked transformer, the input clock pulls down the differential source voltage of the TC latch and the TC multiplexer core while alternating between the two-phase operations. With the enhanced drain-source voltage, the TC design attracts more drain current with less width-to-length ratio of NMOS than that of the CML counterpart. The source-offset voltage is decreased so that the supply voltage can be reduced. The lower supply voltage improves the power consumption and facilitates the integration with low voltage supply SerDes interface. The MUX and the DEMUX chips are fabricated in 65-nm standard CMOS process and operate at 0.7-V supply voltage. The chips are measured up to 40-Gb/s with sub-hundred milliwatts power consumption.

EXISTING SYSTEM:

AS development of the next generation wireless and wire-line communications infrastructure moves forward, the demand of vast data traffic for various applications keeps increasing. Widespread social networking applications flourish in current mobile communication and home networks. The demand of internet bandwidth is increasing dramatically. The fourth generation Long Term Evolution-Advanced (LTE-A) is developed to increase uplink and downlink mobile communication speeds. The basic backbone optical network must increase data transmission rates to meet public demand. The high speed interface to support the system requirements with energy efficiency is still one of the critical issues.

 In 2008, IEEE 802.3ba standard defined the wire-line transmission of 40 gigabit ethernet (40GbE) and 100 gigabit Ethernet (100GbE) [1], [2]. Fig. 1 shows the serializer deserializer (SerDes) interface that supports both data transmission rate of 40-Gb/s and 100-Gb/s [3] with I/O data rate of 10-Gb/s and 25-Gb/s, respectively. At the transmitter side, the 2:1 MUX doubles the input data rate ofMA and MB with the full-rate clock, of which the clock frequency operates at the input data rate. At the receiver side, the 1:2 DEMUX uses the half-rate clock to halve the input data rate of DIN . Besides, the multi-phase clock further slows down the received data with 1: DEMUX (m= 4,8,16……… ) [4]. In this paper, we focus on data converting for the maximum data transmission rate to realize a 2:1 MUX in the transmitter and a 1:2 DEMUX in the receiver.

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PROPOSED SYSTEM:

The contributions of this paper are summarized as follows.

1) The TC technique is first used to the latch design for high speed data processing and to implement the 2:1 MUX and the 1:2 DEMUX in SerDes.

 2) A modified TC circuit is exploited to save one level switching transistor to allow more headroom and to lower supply voltage of the latch and the multiplexer core. The reduced supply voltage lowers the power consumption to sub-hundred milliwatts and facilitates the integration with low supply voltage SerDes interface.

 3) The reduced supply voltage does not lower the output swing in this paper. On the contrary, with our modified TC circuit design, the output swing is enhanced

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SOFTWARE IMPLEMENTATION:

  • Modelsim 6.0
  • Xilinx 14.2

Hardware Implementation:

  • SPARTAN-III, SPARTAN-VI
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