Secure and Efficient data communication protocol for Wireless Body Area Networks

Secure and Efficient data communication protocol for Wireless Body Area Networks

Secure and Efficient data communication protocol for Wireless Body Area Networks

ABSTRACT:

Wireless Body Area Networks (WBANs) are expected to play a major role in the field of patient-health monitoring in the near future, which gains tremendous attention amongst researchers in recent years. One of the challenges is to establish a secure communication architecture between sensors and users, whilst addressing the prevalent security and privacy concerns. In this paper, we propose a communication architecture for BANs, and design a scheme to secure the data communications between implanted /wearable sensors and the data sink/data consumers (doctors or nurse) by employing Ciphertext-Policy Attribute Based Encryption (CP ABE) [1] and signature to store the data in ciphertext format at the data sink, hence ensuring data security. Our scheme achieves a role-based access control by employing an access control tree defined by the attributes of the data. We also design two protocols to securely retrieve the sensitive data from a BAN and instruct the sensors in a BAN. We analyze the proposed scheme, and argue that it provides message authenticity and collusion resistance, and is efficient and feasible. We also evaluate its performance in terms of energy consumption and communication/computation overhead.

PROJECT OUTPUT VIDEO:

EXISTING SYSTEM:

  • As a sensor that collects patient information, all it cares is to distribute the information to authorized doctors and other experts securely. However, there are challenges everywhere: Data should be transmitted in a secure channel, and we all know the challenges in securing wireless communication channels. Node authentication is the most fundamental step towards a BAN’s initial trust establishment, key generation, and subsequent secure communications.
  • There exist research that enables embedded sensors to establish a session key with each other by leverage physiological signals such as Electrocardiograph (ECG).
  • The most relevant existing research along three lines: (1) securing individual (implantable) devices within a BAN; (2) securing the communications within a BAN; and (3) identity-based cryptography for BANs.

DISADVANTAGES OF EXISTING SYSTEM:

  • The key-distribution in symmetric encryption is challenging. And symmetric encryption is not a good choice for broadcasting a message because it involves some challenging issues, such as key-management and access control. At the same time, due to the limitation of memory space in sensors, a data sink, which has considerably larger memory and computation power, is employed to store data.
  • Recent research disclosed that smartphones suffer from severe privacy concerns since many applications often cross the line and read sensitive data at their free will (for example, almost all apps read user’s location).
  • A patient’s IPI information may be remotely captured by an ultra-wide-band (UWB) radar device. This leads to a significant security threat as an adversary with a UWB radar can first capture the IPI and then use it to compromise the patient’s health information.

PROPOSED SYSTEM:

  • We propose a novel encryption and signature scheme based on CP ABE in this paper to address the secure communication problem and provide the required security services mentioned above for BANs.
  • A sensor can control the access to the data it has produced by constructing an access structure. For example, by constructing the access structure (fGWU hospitalg AND fVascular Surgery OR Cardiac Surgeryg), the data requires that only doctors or experts in GWU hospital, Vascular Surgery Center or Cardiac Surgery Center can have the access right.
  • Data are stored in ciphertext format at the data sink and the trust we put on the data sink is now drastically decreased as the data sink does not have the key to decrypt the stored ciphertext. However, the scheme belongs to the asymmetric encryption family, which implies a high computational cost. This problem is addressed by using the scheme to encrypt a session key and then the data is encrypted by symmetric encryption based on the session key.

ADVANTAGES OF PROPOSED SYSTEM:

  • We propose a framework that enables authorized doctors and experts to access a patient’s private medical information securely.
  • Instead of using software or other mechanism to perform access control, we use encryption and signature method to provide a role-based encrypted access control.
  • The sensor has the ability to control who has access to its data by constructing an access structure for the data.
  • We minimize the trust that people usually put on the data sink by storing the data in ciphertext. The compromise of the data stored at the data sink does not necessarily indicate that the data is compromised.
  • We evaluate the performance of the proposed scheme in terms of energy consumption and communication/computation overhead.

SYSTEM ARCHITECTURE:

secure-and-efficient-data-communication-protocol-for-wireless-body-area-networks

SYSTEM REQUIREMENTS:

HARDWARE REQUIREMENTS:

 

  • System : Pentium Dual Core.
  • Hard Disk : 120 GB.
  • Monitor : 15’’ LED
  • Input Devices : Keyboard, Mouse
  • Ram : 1 GB

SOFTWARE REQUIREMENTS:

 

  • Operating system : Windows 7.
  • Coding Language : NET,C#.NET
  • Tool : Visual Studio 2008
  • Database : SQL SERVER 2005

REFERENCE:

Chunqiang Hu, Student Member, IEEE, Hongjuan Li, Xiuzhen Cheng, Fellow, IEEE, Xiaofeng Liao, Senior Member, IEEE, “Secure and Efficient data communication protocol for Wireless Body Area Networks”, IEEE TRANSACTIONS ON MULTI-SCALE COMPUTING SYSTEMS, 2016.

Design and Real-Time Controller Implementation for a Battery-Ultracapacitor Hybrid Energy Storage System

Design and Real-Time Controller Implementation for a Battery-Ultracapacitor Hybrid Energy Storage System

Design and Real-Time Controller Implementation for a Battery-Ultracapacitor Hybrid Energy Storage System

ABSTRACT:

In this work, two real-time energy management strategies have been investigated for optimal current split between batteries and ultracapacitors (UCs) in electric vehicle (EV) applications. In the first strategy, an optimization problem is formulated and solved using Karush-Kuhn-Tucker (KKT) conditions to obtain the real-time operation points of current split for the hybrid energy storage system (HESS). In the second strategy, a neural network based strategy is implemented as an intelligent controller for the proposed system. To evaluate the performance of these two real-time strategies, a performance metric based on the battery state-of-health (SoH) is developed to reveal the relative impact of instantaneous battery currents on the battery degradation. A 38V-385Wh battery and a 32V-4.12Wh UC HESS hardware prototype has been developed and a real-time experimental platform has been built for energy management controller validation, using xPC Target and National Instrument data acquisition system (DAQ). Both the simulation and real-time experiment results have successfully validated the real-time implementation feasibility and effectiveness of the two real-time controller designs. It is shown that under a high speed, high acceleration, aggressive drive cycle US06, the two real-time energy management strategies can greatly reduce the battery peak current and consequently decreases the battery SoH reduction by 31% and 38% in comparison to a battery-only energy storage system.

INTRODUCTION:

          Electric vehicles (EVs) face significant energy storage related challenges, including the range anxiety, high cost, and battery degradation. Batteries, as the energy storage components in majority of current and upcoming EVs, deliver energy to the electric machine during propulsion and recover energy during regenerative braking. For urban drive cycles with frequent stop-and-go, the frequent high power exchange between the electric machine and the ESS results in accelerated battery aging. The battery aging decreases the battery capability of storing energy and providing power over the battery lifetime. One potential solution to this problem is to integrate high-energy (HE) density batteries with high-power (HP) density ultracapacitors (UCs) as hybrid energy storage systems (HESS). UCs has complementary features to batteries with fast charge-discharge, excellent power performance over broad temperature range, long lifetime and high reliability. UCs can protect batteries against fast charging/discharging, reduce high peak power and relieve the battery thermal burden; therefore, prolong the battery lifetime.

 

PROPOSED SYSTEM:

          In this work, two real-time energy management strategies have been investigated for optimal current split between batteries and ultracapacitors (UCs) in electric vehicle (EV) applications. In this work, the semi-active HESS topology is considered. With this topology, the UC pack discharging/charging current Iuc can be controlled through the control of the DC-DC converter. In addition, as the UC pack is decoupled from the dc bus, its voltage can be lower than the dc bus voltage, and consequently the size and cost of UC can be reduced.

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APPLICATIONS:

  • Electric vehicles (EVs).

 

BLOCK DIAGRAM:

821

Control and Implementation of a Standalone Solar Photo-Voltaic Hybrid System

Control and Implementation of a Standalone Solar Photo-Voltaic Hybrid System

Control and Implementation of a Standalone Solar Photo-Voltaic Hybrid System

ABSTRACT:

A control algorithm for a standalone solar photovoltaic (PV)-diesel-battery hybrid system is implemented in this paper. The proposed system deals with the intermittent nature of the energy generated by the PV array and it also provides power quality improvement. The PV array is integrated through a DC-DC boost converter and controlled using a maximum power point tracking (MPPT) algorithm to obtain the maximum power under varying operating conditions. The battery energy storage system (BESS) is integrated to the diesel engine generator (DG) set for the coordinated load management and power flow within the system. The admittance based control algorithm is used for load balancing, harmonics elimination and reactive power compensation under three phase four-wire linear and nonlinear loads. A four-leg voltage source converter (VSC) with BESS also provides neutral current compensation. The performance of proposed standalone hybrid system is studied under different loading conditions experimentally on a developed prototype of the system.

INTRODUCTION:

          Nowadays, the rapid increase in the use of nonlinear loads such as computers, electronics appliances, medical equipment, refrigerators etc. has emphasized the concern for power quality in the electrical distribution system. These loads inject harmonics and distort the current and voltage waveforms causing poor power quality problems. The possible provision for the mitigation of the power quality problems is with inclusion of custom power devices (CPDs). Three-phase four-wire loads are also known to suffer from the problem of neutral current due to non-linearity and unbalance present in the system. This may produce large amount of neutral current which consists of triplen harmonics. The neutral current may cause over-loading of the distribution system and causes additional heat losses which may be dangerous and poses a serious threat to the connected equipment. A four-leg VSC is used for neutral current compensation in addition to mitigate the current harmonics with other reported advantages.

 

PROPOSED SYSTEM:

          The standalone system consists of a PV array along with a boost converter, MPPT controller, diesel engine driven permanent magnet synchronous generator (PMSG), a four-leg VSC with BESS and three-phase four-wire AC loads. The voltage at the point of common coupling is restored by coordinating the reactive power through VSC control. Under varying conditions of generation and loads, BESS offers charging during the daytime when the insolation is large and the load is less. The battery discharges to compensate for any deficits. The DG set operates while maintaining the system frequency under varying generation and loads. The terminal capacitor provides a constant rated terminal voltage at no load. A four leg VSC is interfaced along with its DC bus. The ripple filter and interfacing inductors are used to eliminate the switching harmonics.

 812

ADVANTAGES:

  • Eliminate harmonics, load balancing.
  • Provide neutral current compensation by incorporating four-leg VSC.
  • The ripple filter and interfacing inductors are used to eliminate the switching harmonics.

 

APPLICATIONS:

  • PV-diesel-battery hybrid system.
  • Household appliances.
  • Remote missions.
  • Data communications.
  • Telecommunication systems.
  • Hospitals.
  • Electric aircrafts.
  • Solar cars.

BLOCK DIAGRAM:

811

Geographic and Opportunistic Routing for Underwater Sensor Networks

Geographic and Opportunistic Routing for Underwater Sensor Networks

Geographic and Opportunistic Routing for Underwater Sensor Networks

Geographic and Opportunistic Routing for Underwater Sensor Networks

ABSTRACT:

Underwater wireless sensor networks (UWSNs) have been showed as a promising technology to monitor and explore the oceans in lieu of traditional undersea wireline instruments. Nevertheless, the data gathering of UWSNs is still severely limited because of the acoustic channel communication characteristics. One way to improve the data collection in UWSNs is through the design of routing protocols considering the unique characteristics of the underwater acoustic communication and the highly dynamic network topology. In this paper, we propose the GEDAR routing protocol for UWSNs. GEDAR is an anycast, geographic and opportunistic routing protocol that routes data packets from sensor nodes to multiple sonobuoys (sinks) at the sea’s surface. When the node is in a communication void region, GEDAR switches to the recovery mode procedure which is based on topology control through the depth adjustment of the void nodes, instead of the traditional approaches using control messages to discover and maintain routing paths along void regions. Simulation results show that GEDAR significantly improves the network performance when compared with the baseline solutions, even in hard and difficult mobile scenarios of very sparse and very dense networks and for high network traffic loads.

PROJECT OUTPUT VIDEO: (Click the below link to see the project output video):

EXISTING SYSTEM:

  • Depth-based routing (DBR) routing protocol is the first underwater sensor network routing protocol that uses node depth information to route data packets. The basic idea of DBR is to forward data packets greedily towards the water surface. Thus, packets can reach multiple data sinks deployed at the water surface. During the forwarding, the current sender broadcasts the packet. After receiving it, if the receiver is closer to the water surface, it becomes qualified as a candidate to forward the packet. Otherwise, it will discard the packet.
  • Each qualified candidate will forward the packet in a prioritized manner if its distance to the current forwarder is at least dth and it has not previously sent this packet previously. Node priority is given by means of the holding time. The farther the candidate node is on the current forwarder, the lower is its holding time.
  • After the holding time, the packet is broadcast if the node has not received the same data from a neighbor.

DISADVANTAGES OF EXISTING SYSTEM:

  • This can be expensive in terms of energy since the high energy cost of underwater acoustic communication and the impairments of the acoustic channel.
  • Moreover, as packets will be routed through more hops to circumvent the communication void region, the acoustic channel can be overloaded, increasing the average end-to-end delay and reducing the packet delivery ratio due to more collisions and retransmissions.

PROPOSED SYSTEM:

  • GEDAR is an anycast, geographic and opportunistic protocol that tries to deliver a packet from a source node to some sonobuoys. During the course, GEDAR uses the greedyforwarding strategy to advance the packet, at each hop, towards the surface sonobuoys.
  • A recovery mode procedure based on the depth adjustment of the void node is used to route data packet when it get stuck at a void node. The proposed routing protocol employs the greedy for-warding strategy by means of the position information of the current forwarder node, its neighbors, and the known sonobuoys, to determine the qualified neighbors to continue forwarding the packet towards some sonobuoys.
  • Despite greedy forwarding strategy being a well known and used next-hop forwarder selection strategy, GEDAR considers the anycast nature of underwater routing when multiple surface sonobuoys are used as sink nodes.

ADVANTAGES OF PROPOSED SYSTEM:

  • The works proposed a node’s depth adjustment to improve data packet delivery in static underwater sensor networks.
  • Differently, our node’s depth adjustment algorithm is devoted to the communication void region routing problem in mobile underwater sensor networks, acting in a reactive way to overcome changes in the network topology.
  • Moreover, we implement an opportunistic routing mechanism to mitigate the impairments of the underwater acoustic communication.

SYSTEM ARCHITECTURE:

geographic-and-opportunistic-routing-for-underwater-sensor-networks

SYSTEM REQUIREMENTS:

HARDWARE REQUIREMENTS:

 

  • System : Pentium Dual Core.
  • Hard Disk : 120 GB.
  • Monitor : 15’’ LED
  • Input Devices : Keyboard, Mouse
  • Ram :

SOFTWARE REQUIREMENTS:

 

  • Operating system : Windows XP/UBUNTU.
  • Implementation : NS2
  • NS2 Version : 2.28
  • Front End : OTCL (Object Oriented Tool Command  Language)
  • Tool : Cygwin (To simulate in Windows OS)

REFERENCE:

Rodolfo W. L. Coutinho, Azzedine Boukerche, Luiz F. M. Vieira, and Antonio A. F. Loureiro, “Geographic and Opportunistic Routing for Underwater Sensor Networks”, IEEE TRANSACTIONS ON COMPUTERS, VOL. 65, NO. 2, FEBRUARY 2016.

Isolated Double Step-down DC-DC Converter with Improved ZVS Range and No Transformer Saturation Problem

Isolated Double Step-down DC-DC Converter with Improved ZVS Range and No Transformer Saturation Problem

Isolated Double Step-down DC-DC Converter with Improved ZVS Range and No Transformer Saturation Problem

ABSTRACT:

In this paper, an isolated double step-down DC-DC converter with high efficiency and high step-down function is proposed. The proposed converter employs an additional capacitor in the primary side. Compared to the conventional full-bridge converters, the proposed converter has a double step-down feature with reduced voltage stress at the primary side of the transformer. Moreover, voltage stress of three primary side switches reduces to half of the input voltage and zero voltage switching (ZVS) is naturally achieved for all switches with lower output capacitor energy of the switches. Therefore, the proposed converter requires smaller leakage inductance than the conventional full-bridge converter. Without adding complexity to the hardware and control, the proposed converter inherently prevents transformer saturation problem caused by the DC component of the transformer. A 3-kW experimental prototype is constructed to verify the performance of the proposed converter.

 

INTRODUCTION:

          Nowadays, distributed power system (DPS) is extensively employed in industries, such as telecommunications, computer technology, and information technology, which require high quality and reliability. The DPS generally consists of a power factor correction (PFC) circuit and an isolated DC-DC converter. The DC-DC converter requires both isolation and high step-down conversion ratio from 400 V to 48 V.

PROPOSED SYSTEM:

          In this paper, an isolated double step-down DC-DC converter with high efficiency and high step-down function is proposed. The proposed converter employs an additional capacitor in the primary side.

          The proposed converter has a double step-down feature with reduced voltage stress at the primary side of the transformer. Moreover, voltage stress of three primary side switches reduces to half of the input voltage and zero voltage switching (ZVS) is naturally achieved for all switches with lower output capacitor energy of the switches. Therefore, the proposed converter requires smaller leakage inductance than the conventional full-bridge converter. Without adding complexity to the hardware and control, the proposed converter inherently prevents transformer saturation problem caused by the DC component of the transformer.

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ADVANTAGES:

  • Double step-down function and reduced switch voltage stress.
  • Higher efficiency because the reduced voltage stress enables the proposed converter to operate at a wider ZVS range with reduced switching losses.
  • No transformer saturation problem even when a mismatch exists in the switch duty ratio.

APPLICATIONS:

  • Telecommunications.
  • Computer technology.
  • Information technology.

 

BLOCK DIAGRAM:

iPath: Path Inference in Wireless Sensor Networks

iPath: Path Inference in Wireless Sensor Networks

iPath: Path Inference in Wireless Sensor Networks

ABSTRACT:

Recent wireless sensor networks (WSNs) are becoming increasingly complex with the growing network scale and the dynamic nature of wireless communications. Many measurement and diagnostic approaches depend on per-packet routing paths for accurate and fine-grained analysis of the complex network behaviors. In this paper, we propose iPath, a novel path inference approach to reconstructing the per-packet routing paths in dynamic and large-scale networks. The basic idea of iPath is to exploit high path similarity to iteratively infer long paths from short ones. iPath starts with an initial known set of paths and performs path inference iteratively. iPath includes a novel design of a lightweight hash function for verification of the inferred paths. In order to further improve the inference capability as well as the execution efficiency, iPath includes a fast bootstrapping algorithm to reconstruct the initial set of paths. We also implement iPath and evaluate its performance using traces from large-scale WSN deployments as well as extensive simulations. Results show that iPath achieves much higher reconstruction ratios under different network settings compared to other state-of-the-art approaches. iPath: Path Inference in Wireless Sensor Networks.

PROJECT OUTPUT VIDEO: (Click the below link to see the project output video):

EXISTING SYSTEM:

  • With the routing path of each packet, many measurement and diagnostic approaches are able to conduct effective management and protocol optimizations for deployed WSNs consisting of a large number of unattended sensor nodes. For example, PAD depends on the routing path information to build a Bayesian network for inferring the root causes of abnormal phenomena.
  • Path information is also important for a network manager to effectively manage a sensor network. For example, given the per-packet path information, a network manager can easily find out the nodes with a lot of packets forwarded by them, i.e., network hop spots. Then, the manager can take actions to deal with that problem, such as deploying more nodes to that area and modifying the routing layer protocols.
  • Furthermore, per-packet path information is essential to monitor the fine-grained per-link metrics. For example, most existing delay and loss measurement approaches assume that the routing topology is given as a priori.
  • The time-varying routing topology can be effectively obtained by per-packet routing path, significantly improving the values of existing WSN delay and loss tomography approaches.

DISADVANTAGES OF EXISTING SYSTEM:

  • The growing network scale and the dynamic nature of wireless channel make WSNs become increasingly complex and hard to manage.
  • The problem of existing approach is that its message overhead can be large for packets with long routing paths.
  • Considering the limited communication resources of WSNs, this approach is usually not desirable in practice.

PROPOSED SYSTEM:

  • In this paper, we propose iPath, a novel path inference approach to reconstruct routing paths at the sink side. Based on a real-world complex urban sensing network with all node generating local packets, we find a key observation: It is highly probable that a packet from node and one of the packets from ‘s parent will follow the same path starting from ‘s parent toward the sink. We refer to this observation as high path similarity.
  • The basic idea of iPath is to exploit high path similarity to iteratively infer long paths from short ones. iPath starts with a known set of paths (e.g., the one-hop paths are already known) and performs path inference iteratively. During each iteration, it tries to infer paths one hop longer until no paths can be inferred.
  • In order to ensure correct inference, iPath needs to verify whether a short path can be used for inferring a long path. For this purpose, iPath includes a novel design of a lightweight hash function. Each data packet attaches a hash value that is updated hop by hop. This recorded hash value is compared against the calculated hash value of an inferred path. If these two values match, the path is correctly inferred with a very high probability.
  • In order to further improve the inference capability as well as its execution efficiency, iPath includes a fast bootstrapping algorithm to reconstruct a known set of paths.

ADVANTAGES OF PROPOSED SYSTEM:

  • We observe high path similarity in a real-world sensor network.
  • It’s an iterative boosting algorithm for efficient path inference.
  • It’s a lightweight hash function for efficient verification within iPath.
  • The proposed system further propose a fast bootstrapping algorithm to improve the inference capability as well as its execution efficiency.
  • iPath achieves higher reconstruction ratio under different network settings compared to states of the art.

SYSTEM ARCHITECTURE:

ipath-path-inference-in-wireless-sensor-networks

SYSTEM REQUIREMENTS:

HARDWARE REQUIREMENTS:

 

  • System : Pentium Dual Core.
  • Hard Disk : 120 GB.
  • Monitor : 15’’ LED
  • Input Devices : Keyboard, Mouse
  • Ram :

SOFTWARE REQUIREMENTS:

 

  • Operating system : Windows 7.
  • Coding Language : JAVA/J2EE
  • Tool : Netbeans 7.2.1
  • Database : MYSQL

REFERENCE:

Yi Gao, Student Member, IEEE, Wei Dong, Member, IEEE, Chun Chen, Member, IEEE, Jiajun Bu, Member, IEEE, ACM, Wenbin Wu, and Xue Liu, Member, IEEE, “iPath: Path Inference in Wireless Sensor Networks”, IEEE/ACM TRANSACTIONS ON NETWORKING, VOL. 24, NO. 1, FEBRUARY 2016.

SRAM-Based Unique Chip Identifier Techniques

SRAM-Based Unique Chip Identifier Techniques

ABSTRACT:

Integrated circuit (IC) identification using unclonable digital fingerprints facilitates the authentication of ICs, device tracking, and cryptographic functions. In this paper, we present two hardware methods exploiting the inherent processinduced mismatch of SRAM cells. The proposed circuits improve upon those previously published by reducing the number of bits that vary from trial to trial, and can be used at times other than just IC power-up. The proposed circuits and methods are compared with the previous power-up approach using the experimental results from a 90-nm test chip. The required SRAM array periphery circuit changes allow the use of standard foundry SRAM cells and do not impact the memory access time. The proposed architecture of this paper the area and power consumption are analysis using tanner tools.

 

ENHANCEMENT OF THE PROJECT:

Change the technology based on the power reduction

 

EXISTING SYSTEM:

Nonvolatile Memory Hardware Chip Identification

The most frequently used method of device authentication relies on programming an ID or a digital signature in a nonvolatile (NV) memory block, such as fuses, electrically erasable programmable read-only memory (EEPROM), or flash. NV ID memory has the advantage that the fingerprint is not lost when the device is powered OFF, but the cost of having an NV memory both in terms of area and process added cost precludes this approach in some markets.

Identification Using Physical Unclonable Functions

Another method of generating unique fingerprints is to utilize the inherent process variations in devices to create physically unclonable functions (PUFs). Random variations affect circuit properties, and by constructing the circuits sensitive to those properties, their behavioral differences can be utilized as IC IDs. PUFs using wire delays, gate delays, and ring oscillator frequencies have been proposed. The transistor threshold voltage (VT ) is directly dependent on random dopant fluctuations (RDFs), and is truly random, and thus ideally suited for PUFs. Su et al. proposed a VT mismatch-based identification method using crosscoupled NOR cells. Since RDF is the predominant cause of SRAM mismatch in mature processes, relying on VT strongly suggests using SRAMs for this function.

SRAM Power-Up State as an IC Identifier

SRAM is pervasive on modern ICs. The idea of using existing SRAM states during power-up as a fingerprint of the IC dates back to 2002 and has thoroughly been studied. Commercial SRAMs were powered up numerous times to calculate a statistically repeatable known-ID that was then used to authenticate any other fingerprints generated from further power-ups. Unfortunately, for embedded use, this scheme suffers from the drawbacks that include lack of support for ICs with built-in self-test (BIST) and that the resulting nonmatching codes may have considerably less than ideal code separation. BIST is required in many designs to set redundancy at power-up, which means that the SRAM state will not be random when available to software or hardware normal usage. In addition, the power-up SRAM cell state is influenced by process variations internal to the cell but importantly, by external noise. As the SRAM array is powered up, cells operate in the subthreshold region where they are most easily influenced by noise, potentially producing different power-up states up in different trials.

DISADVANTAGES:

  • Power consumption is high

PROPOSED SYSTEM:

SRAM power-up state was extensively studied as a PUF. All SRAM cells have built-in mismatch due to as-fabricated process variations. The SRAM cell is a crosscoupled inverter pair with a built-in voltage offset (VOFFSET) due to RDFs, i.e., threshold voltage (VT) and other transistor, as well as node capacitance mismatches. Under normal conditions, the SRAM cell’s internal nodes, D and Q, shown in Fig. 2(a), are in one of two stable states DQ = 01 or DQ = 10. States DQ = 11 and 00 are unstable and thus unreachable in the normal operation. When the circuit is powered down (VDD = 0 V), the nodes D and Q are in the unstable 00 state.

Fig. 1. (a) Part of the test SRAM showing the decoder and SRAM array with different power supply voltages used to generate the IDs. Note that the circuit becomes identical to the traditional 6-T structure when VDDARRAY = VDD. (b) Write circuit to implement the BL_Low method. In normal operation, the ID_enable signal is deasserted and the data and its inverse appear on BL and BLN. However, when the ID_enable signal is asserted, both BL and BLN are forced toward VSS.

Proposed Methods and Principle of Operation

In contrast to using power-up, in both the methods proposed here, we force the SRAM into a metastable state (DQ = 11 or DQ = 00), with VDD applied to the SRAM cells. Thus, the SRAM state can be checked at times other than power-up, for instance, after BIST or as requested by a software application.

Fig. 2. (a) BL_High method drives current primarily through the nMOS access and pull-down devices NA0–N0 and NA1–NA1, respectively. (b) SRAM cell internal node (D and Q) waveforms applying the proposed method with both BLs driven to 1 V—BL voltages below show that the BLs cannot reach 1 V due to the strong nMOS pull-down transistors inside the cell. The WL is driven to a higher voltage (1.5 V here) to destabilize the cell and to 1 V, the nominal VDD (1 V here) to read out the value.

The overall operation of a word of SRAM as a PUF is similar to a sense amplifier, whereby the small voltage difference due to VOFFSET is amplified when the cross-coupled inverters are freed after the SRAM cell is driven to a metastable state. To force the nodes D and Q into the metastable state close to 11, the cell must be destabilized. To accomplish this, the access nMOS transistors are strengthened with respect to the pull-down transistors. This is accomplished by altering the voltages at the array level. Thus, the access transistors are made stronger than the pull-down nMOS transistors by increasing their gate overdrive, i.e., setting the word-line (WL) voltage VWL above the array supply voltage VDDARRAY when the fingerprint is taken [see Fig. 1(a)].

Method BL_High (BLs = 1)

For normal applications, the SRAM is read or written by driving the SRAM row WL to VDD = VDDARRAY. To implement the BL_High method, the timing and control circuits are modified to allow the BLs to be precharged, while VWL = VDD > VDDARRAY destabilizes the cell.

Method BL_Low (BLs = 0)

In this proposed method, the BLs are driven toward 0 V by simultaneously writing a logic 0 to each BL. In this scheme, the dominant ratio is that between the pull-up pMOS and the access nMOS transistors, e.g., P0 and NA0, respectively, as shown in Fig. 3(a). In this proposed method, the SRAM cell internal nodes are forced to metastable voltages close, but slightly greater than the 00 power-up point. The SRAM cell is easily destabilized even without the higher voltage on the WL. Therefore, the greater than VDDARRAY VWL voltage is not required.

Fig. 3. (a) BL_Low method drives current primarily through the nMOS access and pull-up pMOS devices NA0 from P0 and NA1 from P1, respectively. (b) Waveforms applying the proposed method with both BLs = 0 V—when driven metastable, the BLs near 0 V, since the pMOS transistors must be weak to ensure normal write-ability.

Circuit Operation

Although in both methods, the SRAM cell is forced to a metastable state, the bit-line voltage amplitude plays a significant role in determining the mismatch in the internal nodes’ VD − VQ (offset) voltage. The SRAM circuits in Figs. 2(a) and 3(a) illustrate the primary current flow through the access transistor NA0 and NA1 that creates the different voltages at nodes D and Q under different BL conditions, projecting the mismatch onto the SRAM cell logical state when the WL is deasserted.

ADVANTAGES:

  • Power consumption is reduced

SOFTWARE IMPLEMENTATION:

  • Tanner tools

An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers

An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers

 

ABSTRACT:

An add-on type real-time jitter tolerance enhancer (JTE) is presented in this paper. The proposed JTE can improve high-frequency jitter tolerance (JTOL) by using a real-time phase alignment scheme. A mathematical analysis for an advanced bit error rate (BER) prediction method is also introduced. The proposed circuit is applicable to various types of receivers, such as referenceless receivers, receivers with a reference clock source, and source-synchronous receivers. The referenceless receiver with the proposed JTE achieved an out-of-band JTOL of 0.71 UIpp at 100 MHz with < 10−12 BER. Total core areas of the receiver and JTE are 0.19 and 0.07 mm2 in a 0.13-µm CMOS process, respectively. The power consumption of the receiver is 38 mW at 5.4 Gbit/s, and the JTE dissipates 22 mW. The proposed architecture of this paper the area and power consumption are analysis using tanner tools.

EXISTING SYSTEM:

Several JTOL-enhancing techniques have been reported in the literature. A gated-digital-controlled oscillator (GDCO)-based clock and data recovery (CDR) circuit were used to enhance JTOL by cascading the high frequency and low-frequency jitter tracking bandwidth (JTB) loops. The semi blind oversampling CDR uses the elastic FIFO to enhance the low-frequency JTOL. A clock-forwarded receiver with injection-locked oscillator (ILO) enhances the JTOL by increasing the JTB. However, the GDCO-based CDR requires an additional frequency calibration circuit in order to minimize its inherent frequency offset. Both the oversampling method and the FIFO incur a large power penalty and the very wide JTB increases unwanted clock jitter. The ILO also requires an additional frequency calibration circuit and a considerably high JTB makes the receiver vulnerable to the noise. Moreover, previous architectures presented in deal with methods to track the input data.

 

DISADVANTAGES:

  • Jitter is produced

 

PROPOSED SYSTEM:

The overall architecture of the receiver with the proposed JTE is shown in Fig. 1. The receiver is composed of an equalizer (EQ), CDR [10], and JTE. The EQ employs an established EQ filter and compensates for the ISI of the input data. The CDR receives the EQ’s output, EQ_OUT, through the 4 delay line. These delay cells help to align the CLKALIGN at the center of the JTE’s delay line, so that the JTE can realign the input data with the maximum alignment range. The CDR operates as follows. First, the frequency detector sets up the VCO’s operating frequency with a random data pattern. Second, the phase detector and charge pump (CP) align CLKSAMPLING to the center of the 4-delayed EQ_OUT. Finally, the recovered clocks (CLK_OUT, CLKSAMPLING, and CLKALIGN) generated by the VCO, and EQ_OUT, are delivered to the JTE. The CDR shown in Fig. 1 is a reference for the JTOL performance comparison.

Fig. 1. Overall block diagram of the receiver with the proposed JTE.

The bottom of Fig. 1 shows a block diagram of the proposed JTE. Unlike the feedback architecture of the phase-aligner.

Equalizer and Delay Line

Fig. 2 shows a detailed block diagram of the EQ and the delay line. The EQ is composed of a continuous time linear EQ (CTLE), limiter, and current mode logic (CML)- to-CMOS converter, as shown in Fig. 2(a). The CML-toCMOS converter output, EQ_OUT, is a full swing signal, which means the JTE is insensitive to the input swing level. However, if the channel loss is too high to maintain the full swing, then the uncompensated ISI jitter from the EQ will be directly inserted to the JTE. In other words, if there are some residual ISI not cancelled by the CTLE, then that ISI will appear at the delay line output and it can be amplified at the worst corner.

Fig. 2. Block diagram of (a) EQ, (b) one delay cell, and (c) schematic of one inverter cell.

Edge Detector

Fig. 3 shows a block diagram of the proposed edge detector (ED). The ED consists of a dual-edge-triggered flip-flop (dual FF), XOR gates, and a selection code holder (SCH).

Fig. 3. Block diagram of the proposed ED.

Phase Selector

After the ED produces the selection code, the phase selector (PS) selects the multiphase data (2Δ, 4 Δ, and 6 Δ). A block diagram of the PS is shown in Fig. 4.

Fig. 4. Block diagram of the PS.

 

ADVANTAGES:

  • reducing the data jitter

 

SOFTWARE IMPLEMENTATION:

  • Tanner tools

Dual-Calibration Technique for Improving Static Linearity of Thermometer DACs for I/O

Dual-Calibration Technique for Improving Static Linearity of Thermometer DACs for I/O

ABSTRACT:

In this paper, we propose a dual-calibration technique to improve the matching accuracy of digital-to-analog converter (DAC) elements and improve nonlinearity induced static errors in a current-steering thermometer DAC. The novelty of the proposed dual-calibration scheme lies in obtaining best samples from the error distribution using redundancy for improved matching followed by adaptively reordering these samples to reduce error accumulation. This technique exploits the 2-D nature of the DAC to achieve lower calibration time. We consider the statistical basis for each of these methods and demonstrate statistical modeling of the proposed technique. We demonstrate a 38% reduction in differential nonlinearity (DNL) and 55% reduction in integral nonlinearity (INL) through simulations. We fabricated an 8-bit current steering thermometer DAC in Taiwan Semiconductor Manufacturing Company 65-nm CMOS process. With only 2 redundant cells per row, we show an improvement of 36% in DNL and 50% in INL from the measurement of 16 chips over the baseline DAC. The proposed architecture of this paper the area and power consumption are analysis using tanner tools.

 

ENHANCEMENT OF THE PROJECT:

Change the technology based on the error reduction.

 

EXISTING SYSTEM:

As transistor sizes decrease with the scaling of CMOS processes, the area of a DAC’s unit cell and the overall DAC area also decrease. However, for a given process, matching accuracy among the unit cells is inversely proportional to area. This implies that unit cells need to be made larger to overcome the detrimental effect of increased nonlinearity and to maintain yield. Various preprocessing techniques such as special layout implementations, and biasing and routing schemes have been used to compensate for this loss in accuracy without growing the unit cells. These approaches are good for removing systematic geometric errors. However, they are not able to eliminate random mismatch errors that are becoming dominant in lower feature sizes. Hence, calibration becomes essential.

Calibration schemes for thermometer DACs fall mainly into two categories—trimming and switching. Trimming-based calibration methods focus on decreasing the mismatch error by calibrating each current source to a reference current using a calibration DAC. The issue with most of these schemes is the large amount of area added to the unit cells in the form of additional circuitry that does not scale well with process. Switching-based calibration methods focus on minimizing error accumulation by achieving mismatch error cancellation with successive addressing. Methods like dynamic element matching, which also increases the noise floor, and dynamic mismatch mapping, target dynamic linearity and do not reduce the overall power of the mismatch error that is important for improving the static linearity. Many other switching schemes use complex optimization algorithms requiring higher calibration time and power. In addition, no significant reduction in the mismatch error itself is achieved by the existing switching-based techniques.

DISADVANTAGES:

  • Mismatch between the DAC’s unit elements

 

PROPOSED SYSTEM:

Fig. 1. Complete 8-bit dual-calibrated thermometer DAC architecture with all the calibration blocks and modified unit cell (shaded blocks used only during calibration).

The complete dual-calibrated DAC architecture is shown in Fig. 1. The calibration proceeds as follows. First, determine the median using the median detection block. Second, find the outliers in each row by first converting the analog current values from each cell and the median current to digital words. Next, calculate the absolute difference between the median value and the unit cell values and denote the two cells per row with the maximum absolute difference as the outliers. Following the outlier determination process, convert the summed row currents of the outlier-free DAC into digital words.

Median Detection

To determine the median current, we estimate the median value by comparing the current from the median cell (Fig. 2) with the current from each of the unit cells. The median cell is tuned to an output current such that the number of DAC unit cells with currents higher than the median cell’s is equal to the number of DAC unit cells with lower currents.

Fig. 2. Median detection circuit

Analog-to-Digital Conversion

Fig. 3. CSRO-ADC.

For both the methods involved in the dual-calibration technique, we convert the analog current values into digital words and then calculate the difference from the median and the ranking of rows in digital domain as it is done in many of the switching-based calibration techniques. Low-resolution analog-to-digital conversion is performed using a 6-bit current starved ring oscillator-analog-to-digital converter (CSRO-ADC), as shown in Fig. 3.

Design of DAC Unit Cell

Once the outliers for each row of the DAC have been determined, this information is stored in the unit cells as a valid bit (VB). The proposed DAC cell is similar to a standard single-ended DAC cell except for the additional memory to store the VB, as shown in Fig. 8. The memory is a standard 6T static random access memory (SRAM), along with a separate readout switch.

Fig. 4. (a) Column selection decoder. (b) Row selection decoder

Column Selection Decoder

The column decoder maps the column bits of the DAC via a binary-to-thermometer decoder, as shown in Fig. 4(a). Because of the redundant and invalid cells, the decoder also must consider the status stored in the memories of the cells in a row. If a cell is invalid, then it must be skipped by the decoder.

Row Selection Decoder

Due to the reordering of the rows, instead of a standard binary-to-thermometer decoder, a row selection decoder is used that consists of digital comparators and a memory bank of 16 4-bit SRAMs, where once the ranks of the rows have been determined, the order is stored. Each row rank is written sequentially, requiring 16 address cycles for this operation. For each row in the DAC, row selection decoder has two outputs—next Row and Row. During the DAC operation, the incoming row bits, rb are compared with the stored ranks using digital comparators, as shown in Fig. 4(b), to switch on the appropriate rows. For rows with rank > rb, Next Row is high and for rows with rank ≥ rb, Row is set high.

ADVANTAGES:

  • Improve the static linearity
  • Reduce the error

SOFTWARE IMPLEMENTATION:

  • Tanner tools

Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization

Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization

ABSTRACT:

Ultralow-power subthreshold logic circuits are becoming prominent in embedded applications with limited energy budgets. Minimum energy consumption of digital logic circuits can be obtained by operating in the subthreshold regime. However, in this regime process variations can result in up to an order of magnitude variations in ION/IOFF ratios leading to timing errors, which can have a destructive effect on the functionality of the subthreshold circuits. These timing errors become more frequent in scaled technology nodes where process variations are highly prevalent. Therefore, mechanisms to mitigate these timing errors while minimizing the energy consumption are required. In this paper, we propose a tunable adaptive feedback equalizer circuit that can be used with a sequential digital logic to mitigate the process variation effects and reduce the dominant leakage energy component in the subthreshold digital logic circuits. We also present detailed energy-performance models of the adaptive feedback equalizer circuit. As part of the modeling approach, we also develop an analytical methodology to estimate the equivalent resistance of MOSFET devices in subthreshold regime. For a 64-bit adder designed in 130 nm, our proposed approach can reduce the normalized variation of the critical path delay from 16.1% to 11.4% while reducing the energy-delay product by 25.83% at minimum energy supply voltage. The proposed architecture of this paper the area and power consumption are analysis using tanner tools.

PROJECT OUTPUT VIDEO: (Click the below link to see the project output video):

ENHANCEMENT OF THE PROJECT:

Use different combinational circuits.

EXISTING SYSTEM:

Combinational logic refers to circuits whose output is strictly depended on the present value of the inputs. As soon as inputs are changed, the information about the previous inputs is lost, that is, combinational logics circuits have no memory. In many applications, information regarding input values at a certain instant of time is required at some future time. Although every digital system is likely to have combinational circuits, most systems encountered in practice also include memory elements, which require that the system be described in terms of sequential logic. Circuits whose outputs depend not only on the present input value but also the past input value are known as sequential logic circuits. The mathematical model of a sequential circuit is usually referred to as a sequential machine.

An edge-triggered flip-flop changes states either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock pulse on the control input. The three basic types are introduced here: S-R, J-K and D.

The S-R, J-K and D inputs are called synchronous inputs because data on these inputs are transferred to the flip-flop’s output only on the triggering edge of the clock pulse. On the other hand, the direct set (SET) and clear (CLR) inputs are called asynchronous inputs, as they are inputs that affect the state of the flip-flop independent of the clock. For the synchronous operations to work properly, these asynchronous inputs must both be kept LOW.

Subthreshold digital circuits suffer from the degraded ION/IOFF ratios resulting in a failure in providing rail-to-rail output swings when restricted by aggressive timing constraints. These degraded ION/IOFF ratios and process-related variations make subthreshold circuits highly susceptible to timing errors that can further lead to complete system failures. Since the standard deviation of VT varies inversely with the square root of the channel area, one approach to overcome the process variation is to upsize the transistors. Alternately, one can increase the logic path depth to leverage the statistical averaging of the delay across gates to overcome process variations. These approaches, however, increase the transistor parasitics, which in turn increases the energy consumption. In this paper, we first propose the use of a feedback equalizer circuit for lowering the energy consumption of digital logic operating in the subthreshold region while achieving robustness equivalent to that provided. Here, the feedback equalizer circuit (placed just before the flip-flop) adjusts the switching threshold of its inverter based on the output of the flip-flop in the previous cycle to reduce the charging/discharging time of the flip-flop’s input capacitance. Moreover, the smaller input capacitance of the feedback equalizer reduces the switching time of the last gate in the combinational logic block. Overall, this reduces the total delay of the sequential logic, which makes it more robust to timing errors and allows aggressive clocking to reduce the dominant leakage energy. In addition to reducing energy consumption, we also demonstrate how the tuning capability of the equalizer can be used to enable extra charging/discharging paths for the flip-flop input capacitance after fabrication to mitigate timing errors resulting from worse than expected process variations in the subthreshold digital logic.

DISADVANTAGES:

  • Energy efficiency is less
  • Transition time is high

PROPOSED SYSTEM:

Fig. 1. Adaptive feedback equalizer circuit with multiple feedback paths (designed using a variable threshold inverter ) can be combined with a traditional master–slave flip-flop to design an adaptive E-flip-flop.

We first explain the use of the adaptive feedback equalizer circuit in the design of an adaptive equalized flip-flop (E-flip-flop) and then provide a detailed comparison of the E-flip-flop with the conventional flip-flop in terms of area, setup time, and performance. We propose the use of a variable threshold inverter (Fig. 1) as an adaptive feedback equalizer along with the classic master–slave positive edge-triggered flip-flop (Fig. 2) to design an adaptive E-flip-flop. This adaptive feedback equalizer circuit consists of two feedforward transistors (M1 and M2 in Fig. 1) and four control transistors (M3 and M4 for feedback path 1 that is always ON and M5 and M6 for feedback path 2 that can be conditionally switched ON postfabrication in Fig. 1) that provide extra pull-up/pull-down paths in addition to the pull-up/pull-down path in the static inverter for the Data FlipFlop input capacitance.

Fig. 2. Circuit diagram of classic master–slave positive edge-triggered flip-flop

e analyze the capability of the adaptive feedback equalizer circuit to reduce the transition time of the last gate in critical path of the subthreshold logic and make a comparison with the original nonequalized design, and the buffer-inserted nonequalized design (Fig. 3). The classic buffer insertion technique [Fig. 3(c)] will reduce the total delay along critical path of the subthreshold logic. Like the gates in the combinational logic, the buffer used in Fig. 3(c) is upsized to account for the process variation effects based on the design methodology proposed.

Fig. 3. Block diagrams of (a) original nonequalized design, (b) equalized design with one feedback path ON, and (c) buffer-inserted nonequalized design.

MODELING OF FEEDBACK EQUALIZER CIRCUITS

We present detailed AMs for the performance and the energy of adaptive equalizer circuits operating in the subthreshold regime. Using these models, we determine the sizes for feedforward transistors and control transistors in the feedback equalizer circuit that minimize total delay and leakage energy for the equalized subthreshold logic. Without loss of generality, we choose minimum-sized transistors for matching high-to-low and low-to-high propagation delay in the static inverter of the feedback equalizer circuit. As part of the effort, we first develop an analytical methodology to calculate the equivalent channel resistance of active MOSFET devices operating in the subthreshold regime. The proposed model is validated against HSPICE simulations (HSs) using UMC 130-nm process.

ADVANTAGES:

  • improve energy efficiency
  • mitigate process variation effects
  • transition time is reduced

SOFTWARE IMPLEMENTATION:

  • Tanner tools